SSTE32882KA1 Integrated Device Technology, SSTE32882KA1 Datasheet - Page 11

no-image

SSTE32882KA1

Manufacturer Part Number
SSTE32882KA1
Description
1.25v/1.35v/1.5v Registering Clock Driver With Parity Test And Quad Chip Select
Manufacturer
Integrated Device Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTE32882KA1AKG
Manufacturer:
IDT
Quantity:
20 000
Function Table (Each Flip Flop) with QuadCS Mode Disabled
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
Power
RESET
Signal Group
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
H
H
H
H
H
H
L
1
2
RESET is driven HIGH.
3
4
5
6
7
disabled independent of control word RC0 once 3T timing is activated.
1
2
3
Q
It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and HIGH) when
ADDR = DA[15:0], DBA[2:0]
CTRL = DODTn, DCKEn.
Qn = QxAn, QxRAS, QxCAS, QxWE, and QxBAn.
1.25V/1.35V/1.5V CMOS inputs use V
CMD = DRAS, DCAS, DWE.
Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state (Q
These outputs are optimized for memory applications to drive DRAM inputs to 1.25V/1.35V/1.5V signaling levels.
Voltage levels according standard JESD8-11A, wide range, non terminated logic.
0
DCS0
X or
float
means the output does not change state.
X
X
H
H
L
L
Vrefca
Vdd
Vss
AVdd
AVss
PVdd
PVss
RSVD
DCS1
X or
float
Signal Name
X
H
X
H
L
L
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
1
L or H H or L
X or
float
CK
Inputs
L
2
X or
float
CK
L
Reference Voltage
Register Power
Register Ground
Analog Power
Analog Ground
PLL Power
PLL Ground
I/O
2
Control
ADDR
REFCA
Word
X or
float
X or
float
Type
X
X
X
X
3
as the switching point reference for these receivers.
X or float
X or float
Control
CMD
Word
X
X
X
X
Input reference voltage for the differential data inputs, V
(0.75V) nominal.
Power supply voltage (Register)
Ground (Register)
Analog supply voltage (PLL)
Analog ground (PLL)
Clock logic and clock output driver power supply (PLL)
Clock logic and clock output driver ground (PLL)
Reserved pins, must be left floating (PLL)
4
Control
CTRL
Word
X or
float
X
X
X
X
X
5
Follows
Follows
float
Input
Input
Q
float
float
Qn
Q
Q
0
0
0
or
6
11
7
QxCS0
float
float
Description
Q
H
H
H
L
0
0
) is maintained. Address floating is
COMMERCIAL TEMPERATURE RANGE
QxCS1
float
float
Outputs
Q
SSTE32882KA1
H
H
H
L
0
1
QxODTn
Follows
Follows
Follows
Input
Input
Input
float
float
Q
Q
0
0
DD
QxCKEn
/2
Follows
Follows
Follows
Input
Input
Input
Q
Q
L
L
0
0
7314/8

Related parts for SSTE32882KA1