ds3908nt-r Maxim Integrated Products, Inc., ds3908nt-r Datasheet - Page 9

• Manufacturer Part Number: ds3908nt-r
• Description: Ds3908 Dual 64-position Nonvolatile Digital Potentiometer With Buffered Output
• Manufacturer: Maxim Integrated Products, Inc.

The following terminology is commonly used to describe
I
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, and start and stop conditions.
Slave Devices: Slave devices send and receive data at
the master’s request.
Bus Idle or not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a stop condition. See the timing diagram for applicable
timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer to
indicate that it will immediately initiate a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start
condition. See the timing diagram for applicable timing.
Figure 2. I
2
C data transfers:
SDA
SCL
NOTE: TIMING IS REFERENCE TO V
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C Serial Interface Description
2
C Timing Diagram
STOP
t
BUF
START
IL(MAX)
Potentiometer with Buffered Outputs
t
HD:STA
AND V
t
LOW
Dual, 64-Position Nonvolatile Digital
IH(MIN)
.
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_____________________________________________________________________
C Definitions
t
R
t
HD:DAT
t
F
t
HIGH
t
SU:DAT
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold-time requirements (see Figure 2). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (see Figure 2) before the next rising edge of
SCL during a bit read. The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An Acknowledge-
ment (ACK) or Not Acknowledge (NACK) is always the
9th bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave dur-
ing a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one during the 9th bit. Timing (Figure 2)
for the ACK and NACK is identical to all other bit writes.
An ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a read
sequence or as an indication that the device is not
receiving data.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
REPEATED
START
t
SU:STA
t
HD:STA
t
SP
t
SU:STO
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