isl6296a Intersil Corporation, isl6296a Datasheet - Page 16

• Manufacturer Part Number: isl6296a
• Description: Flexihash? For Battery Authentication
• Manufacturer: Intersil Corporation

ADDRESS 0-06/07/08/09: AUTHENTICATION SECRET
SET #2 (SE2A/B/C/D)
These address locations store the second set of secrets to
be used for hash calculation. Reading and writing to this
register can be disabled by setting the SLO[1] bit at OTP
ROM location 0-00[1].
BIT
BIT
3:2
1:0
5:2
7
6
1
0
7
6
5
4
DAB[1:0]
SLO[1:0]
NAME
NAME
eEEW
sEEW
SRST
sACC
ASLP
sBER
eINT
--
--
TYPE
TYPE
RW
RW
WC
RC
RC
RC
R
R
R
R
R
16
DEFAULT
DEFAULT
<1/0>
<00>
<00>
<1>
<1>
00
00
0
0
0
0
0
0
0
0
0
TABLE 14. MASTER CONTROL REGISTER (MSCR)
OTP ROM Write-in-Progress Interrupt Enable: When enabled, it allows the sEEW bit to flag an
interrupt whenever the sEEW bit is set by its interrupt event. The eEEW bit is fixed at ‘1’ when none
of the OTP ROM lock-out bits are set. When any or both of the lock-out bits are set, the eEEW bit
will become permanently ‘0’ after a reset.
Global Interrupt Enable: When enabled, it allows the sBER or sACC bit to flag an interrupt to the
host whenever any of the respective interrupt events occurred.
(Default setting loaded from OTP ROM location 0-00[3])
Unused.
Auto Sleep Mode enable: When set, the ISL6296A will automatically enter Sleep mode after about
1s of XSD bus inactivity. When cleared, the device can only enter Sleep mode on Opcode
command.
(Default setting loaded from OTP ROM location 0-00[2])
Soft Reset: When a ‘1’ is written and all registers are reset to their default states, all bus counters
and timers are reset to their start-up conditions and device configuration information is reloaded
from OTP ROM. After the reset sequence is complete, a ‘break’ pulse is sent to the host.
OTP ROM Write-in-Progress Flag: This bit is set when attempt is made by the host to read from or
write to the ISL6296A while the ROM is still processing the previous write instruction.
XSD Bus Error Flag: This bit is set when one or more of the following occurrs at the bus interface:
a) An invalid pulse width is received
b) Bus activity is detected before the device completes its power-up sequence
c) An invalid BYTES field in the instruction frame
d) Improper authentication sequence is detected
e) Reading secret information after the corresponding lock-out bits are set
protected register as follows:
a) Writing to OTP ROM after the ISL6296A has been locked out (any or both of the lock-out bits set)
b) Accessing the ISL6296A is Test and Trim Registers when the device is not in test mode
Unused
Device Address Bit Setting:
Loaded from OTP ROM location 0-00[7:6] during power-up.
Secrets Lock-out Bits Setting:
Loaded from OTP ROM location 0-00[1:0] during power-up.
Register Access Error Flag: This bit is set whenever an instruction frame attempts to access a
TABLE 15. DEVICE STATUS REGISTER (STAT)
ISL6296A
ADDRESS 0-0A/0B/0C/0D: AUTHENTICATION SECRET
SET #3 (SE3A/B/C/D)
These address locations store the optional third set of
secrets to be used for hash calculation. Reading and writing
to this register can be disabled by setting the SLO[0] bit at
OTP ROM location 0-00[0].
Alternately, this memory space can be used to store
additional cell information which can be accessed by the
host. In this case, the SLO[0] bit should not be set.
DESCRIPTION
DESCRIPTION
October 31, 2007
FN6567.0