isl6262a Intersil Corporation, isl6262a Datasheet - Page 24

• Manufacturer Part Number: isl6262a
• Description: Two-phase Core Controller Santa Rosa, Imvp-6+
• Manufacturer: Intersil Corporation

To achieve the droop value independent from the
temperature of the inductor, it is equivalently expressed by
Equation 21.
The non-inverting droop amplifier circuit has the gain
K
G
Therefore, the temperature characteristics of gain of Vn is
described by Equation 22.
For the G
R
R
R
RS
feature specified in Equation 22.
The actual G1 at +25°C is 0.769. For different G1 and NTC
thermistor preferences, the design file to generate the proper
value of R
Intersil.
Then, the individual resistors from each phase to the VSUM
node, labeled R
Equation 23.
So, R
and R
gain required to achieve the load line. Setting
R
Droop Impedance (R
IMVP-6+ specification, DCR = 0.0008Ω typical for a 0.36µH
inductor, R
R
Note, we choose to ignore the R
not add significant error.
These designed values in R
the layout and coupling factor of the NTC to the inductor. As
only one NTC is required in this application, this NTC should
be placed as close to the Channel 1 inductor as possible and
R
G
k
G
R
Rdrp2
Rdrp2
droopamp
droopamp
ntc
series
par
drp1
drp2
droop
1target
S
1
1
T ( )
T ( )
EQV
=
= 10kΩ with b = 4300,
= 11kΩ
s
2 RS
N
•
= 1k_1%, then R
is then given by Equation 25.
=
= 3650Ω. Once we know the attenuation of the R
=
=
= 2.61kΩ, and
•
=
(
= 1825Ω generates a desired G1, close to the
network, we can then determine the droop amplifier
1
is the desired gain of Vn over I
------------------------------------------------------ -
(
⎛
⎝
⎛
⎝
1target
1
G
+
ntc
----------------------------------------------- 1
DCR G1 25°C
-------------------------------------- - 1
0.0008 0.769
drp1
expressed as:
=
+
1
0.00393*(T-25)
EQV
2 R
T ( )
, R
0.00393*(T-25)
1
2 R
•
G
+
•
= 1kΩ and the attenuation gain (G1) = 0.77,
•
series
S1
•
1t
= 0.76:
R
--------------- -
R
droop
•
DCR
-------------------
arg
drp2
drp1
droop
and R
(
2
et
droop
, R
25
drp2
par
–
•
S2
)
)
(
) = 0.0021 (V/A) as per the Intel
⎞
⎠
, and RS
≅
)
–
1
can be found using Equation 24.
in Figure 37, are then given by
n
•
G
+
24
⎞
⎠
1kΩ
network are very sensitive to
1t
0.00393*(T-25)
•
arg
O
R
drp1
≈
resistors because they do
et
EQV
5.82kΩ
OUT
is provided by
) k
• DCR/2.
•
droopamp
(EQ. 20)
(EQ. 21)
(EQ. 23)
(EQ. 25)
(EQ. 22)
(EQ. 24)
S
ISL6262A
PCB traces sensing the inductor voltage should be going
directly to the inductor pads.
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This is fairly
easy and can be accomplished by allowing the system to
achieve thermal equilibrium at full load, and then adjusting
R
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 2.1mV/A load line should be adjusted by R
on maximum current, (not based on small current steps like
10A), as the droop gain might vary between each 10A step.
Basically, if the max current is 40A, the required droop
voltage is 84mV. The user should have 40A load current on
and look for 84mV droop. If the drop voltage is less than
84mV, for example 80mV, the new value will be calculated
by: using Equation 26.
For the best accuracy, the effective resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the previous example, the resistance on the DFB pin is
R
or 853Ω. The resistance on the VSUM pin is R
with RS
mismatch in the effective resistances is 1404 - 53 = 551Ω.
Do not let the mismatch get larger than 600Ω. To reduce the
mismatch, multiply both R
factor. The appropriate factor in the example is
1404/853 = 1.65. In summary, the predicted load line with
the designed droop network parameters based on the
Intersil design tool is shown in Figure 41
Rdrp2_new
drp2
drp1
to obtain the appropriate load line slope.
in parallel with R
EQV
=
or 5.87k in parallel with 1.825k or 1392Ω. The
84mV
--------------- - Rdrp1
80mV
(
drp2
drp1
, that is, 1k in parallel with 5.82k
+
Rdrp2
and R
) Rdrp1
–
drp2
by the appropriate
n
December 23, 2008
drp2
in parallel
based
(EQ. 26)
FN6343.1