isl6252a Intersil Corporation, isl6252a Datasheet
isl6252a
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isl6252a Summary of contents
Page 1
... Ld 5x5 QFN L28.5×5 ISL6252HAZ* ISL 6252HAZ -10 to +100 24 Ld QSOP ISL6252AHRZ* ISL6252 AHRZ -10 to +100 28 Ld 5x5 QFN L28.5×5 ISL6252AHAZ* ISL6252 AHAZ -10 to +100 24 Ld QSOP NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets ...
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... VREF 7 CHLIM ISL6252, ISL6252A CSOP 20 CSIN 19 CSIP PHASE 16 15 UGATE 13 14 ISL6252, ISL6252A (24 LD QSOP) TOP VIEW VDD DCIN 1 24 ACSET 2 23 ACPRN EN CSON 3 22 CELLS 4 21 CSOP ICOMP 5 20 CSIN VCOMP CSIP 6 19 ICM ...
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... ISL6252, ISL6252A ACSET ACPRN + - 1.26V VREF 152kΩ ADAPTER CURRENT ACLIM LIMIT SET 152kΩ ICOMP MIN VOLTAGE BUFFER VCOMP VREF 514kΩ gm1 - VADJ 514kΩ 2.1V VOLTAGE CELLS SELECTOR VDD REFERENCE VREF GND FB FIGURE 1. FUNCTIONAL BLOCK DIAGRAM 3 ICM CSIP CSIN ...
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... TRICKLE TRICKLE TRICKLE TRICKLE CHARGE CHARGE CHARGE CHARGE FIGURE 2. ISL6252, ISL6252A TYPICAL APPLICATION CIRCUIT WITH FIXED CHARGING PARAMETERS 4 ISL6252, ISL6252A 0.1µF CSON R21 2.2Ω CSIP CSIP CSIP CSIP ISL6252 ISL6252 ISL6252 ISL6252 0.1 0.1µ ...
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... C5 4.7k 10nF SCL SCL SCL SCL SDL SDL SDL SDL A/D INPUT A/D INPUT A/D INPUT A/D INPUT GND GND GND GND FIGURE 3. ISL6252, ISL6252A TYPICAL APPLICATION CIRCUIT WITH µP CONTROL 5 ISL6252, ISL6252A C8 C8 0.1 0.1 0.1µF 0.1 CSON DCIN DCIN DCIN R21 2.2Ω CSIP CSIP CSIP ACSET ACSET ...
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... TRIP POINTS ACSET Threshold ACSET Input Bias Current Hysteresis ACSET Input Bias Current ACSET Input Bias Current 6 ISL6252, ISL6252A Thermal Information Thermal Resistance QFN Package (Notes 4, 5 QSOP Package (Note Junction Temperature Range .-10°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65° ...
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... CSOP to CSON Full-Scale Current Sense Voltage ISL6252A CSOP to CSON Full-Scale Current Sense Voltage ISL6252 CSOP to CSON Full-Scale Current Sense Voltage formula ISL6252A CSOP to CSON Full-Scale Current Sense Voltage formula CHLIM Input Bias Current CHLIM Power-Down Mode Threshold Voltage CHLIM Power-Down Mode Hysteresis Voltage ...
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... Thermal Shutdown Temperature Hysteresis NOTE: 6. This is the sum of currents in these pins (CSIP, CSIN, BOOT, UGATE, PHASE, CSOP, CSON) all tied to 16.8V. No current in pins EN, ACSET, VADJ, CELLS, ACLIM, CHLIM. 8 ISL6252, ISL6252A TEST CONDITIONS ACLIM = VREF ACLIM = Float ACLIM = GND ACLIM = VREF ACLIM = GND ...
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... CSIP-CSIN (mV) FIGURE 6. ACCURACY vs AC ADAPTER CURRENT FIGURE 8. AC AND DC ADAPTER DETECTION 9 ISL6252, ISL6252A DCIN = 20V, 4S2P Li-Battery, T 0.10 0.08 0.06 0.04 0.02 0. 100 100 FIGURE 7. SYSTEM EFFICIENCY vs CHARGE CURRENT DCIN DCIN 10V/div 10V/div ACSET ...
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... CHLIM = 0.2V CHLIM=0.2V CHLIM=0.2V CSON = 8V CSON=8V CSON=8V FIGURE 12. AC ADAPTER REMOVAL ADAPTER REMOVAL ADAPTER REMOVAL ADAPTER REMOVAL FIGURE 14. SWITCHING WAVEFORMS AT DIODE EMULATION 10 ISL6252, ISL6252A DCIN = 20V, 4S2P Li-Battery +25°C, Unless Otherwise Noted. (Continued) A CSON CSON 5V/div 5V/div EN EN 5V/div 5V/div INDUCTOR ...
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... GND is an analog ground. DCIN The DCIN pin is the input of the internal 5V LDO. Connect it to the AC adapter output. Connect a 0.1µF ceramic capacitor from DCIN to CSON. 11 ISL6252, ISL6252A DCIN = 20V, 4S2P Li-Battery +25°C, Unless Otherwise Noted. (Continued) A FIGURE 16. TRICKLE TO FULL-SCALE CHARGING ACSET ACSET adapter detection input ...
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... Do not connect a decoupling capacitor. Theory of Operation Introduction Unless otherwise noted, all descriptions of ISL6252 refer to both ISL6252 and ISL6252A. The ISL6252 includes all of the functions necessary to charge cell Li-Ion and Li- polymer batteries. A high efficiency synchronous buck converter is used to control the charging voltage and charging current up to 10A ...
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... MAX CSOP CSON ( 2 MIN CSOP CSON With CHLIM = 1.5V, the maximum CSOP-CSON voltage is 78mV and the minimum CSOP-CSON voltage is 72mV. When ISL6252A is in charge current limiting mode, the maximum charge current is the maximum CSOP-CSON V ⎛ ⎞ ⎛ ⎞ 165mV CHLIM ------------------- ...
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... This can be calculated for ISL6252A with Equation 7: ISL6252A ( • ⁄ CHLIM 50.28 + 2.4 , CHG MAX 1MIN ( • ⁄ I CHLIM 49.72 2.4 = – , CHG MIN 1MAX Maximum charge current can be calculated for ISL6252 with Equation 8: ISL6252 ( • ⁄ I CHLIM ...
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... ADJ ADJ V = 12.6V and V =12.693V or OUT,NOM OVP V + 93mV. OUT,NOM 15 ISL6252, ISL6252A There is a delay of approximately 400nsec between V exceeding the OVP trip point and pulling VCOMP, LGATE and UGATE low. VCOMP ICOMP BATTERY REMOVAL PHASE FIGURE 17. OVERVOLTAGE PROTECTION IN ISL6252 Application Information The following battery charger design refers to the typical application circuit in Figure 2, where typical battery configuration of 4S2P is used ...
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... Organic polymer capacitors have high capacitance with small size and have a significant equivalent series resistance (ESR). Although 16 ISL6252, ISL6252A ESR adds to ripple voltage, it also creates a high frequency zero that helps the closed loop operation of the buck (EQ. 17) regulator ...
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... One option is to choose a combined MOSFET with the Schottky diode in a single package. The integrated packages may work better in 17 ISL6252, ISL6252A practice because there is less stray inductance due to a short connection. This Schottky diode is optional and may be removed if efficiency loss can be tolerated. In addition, ensure that the required total gate drive current for the selected MOSFETs should be less than 24mA ...
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... Which loop controls the output is determined by the minimum current buffer and the minimum voltage buffer shown in Figure 1. These three loops will be described separately. 18 ISL6252, ISL6252A TRANSCONDUCTANCE AMPLIFIERS GM1, GM2 AND GM3 ISL6252 uses several transconductance amplifiers (also known as gm amps). Most commercially available op amps ...
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... FILTER 2π The cross over frequency is determined by the DC gain of the modulator and output filter and the pole in Equation 23. 19 ISL6252, ISL6252A The DC gain is calculated in Equation 34 and the cross over frequency is calculated with Equation 35 (EQ. 30 The bode plot of the loop gain, the compensator gain and ...
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... R VCOMP FIGURE 22. VOLTAGE CONTROL LOOP Output LC Filter Transfer Functions The gain from the phase node to the system output and battery depend entirely on external components. Typical 20 ISL6252, ISL6252A output LC filter response is shown in Figure 23. Transfer function A and the duty cycle and the ...
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... VCOMP 0.3 f 2π VCOMP 21 ISL6252, ISL6252A PCB Layout Considerations f LC Power and Signal Layers Placement on the PCB f POLE1 As a general rule, power layers should be close together, either on the top or bottom of the board, with signal layers on the opposite side of the board example, layer arrangement on a 4-layer board is shown below: 1 ...
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... KELVIN CONNECTION TRACES TO THE LOW PASS FILTER AND CSOP AND CSON FIGURE 25. CURRENT SENSE RESISTOR LAYOUT 22 ISL6252, ISL6252A EN Pin This pin stays high at enable mode and low at idle mode and is relatively robust. Enable signals should refer to the signal ground. DCIN Pin This pin connects to AC adapter output voltage, and should be less noise sensitive ...
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... CORNER REF. OPTION 4X BOTTOM VIEW SECTION "C-C" TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 23 ISL6252, ISL6252A L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE SYMBOL 0.10 C 0.08 C ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 24 ISL6252, ISL6252A M24.15 24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE M ...