isl6228 Intersil Corporation, isl6228 Datasheet - Page 11

• Manufacturer Part Number: isl6228
• Description: High-performance Dual-output Buck Controller For Notebook Applications
• Manufacturer: Intersil Corporation

Programming the PWM Switching Frequency
The ISL6228 does not use a clock signal to produce PWMs.
The PWM switching frequency f
resistor R
GND pin. The approximate PWM switching frequency is
written as Equation 10:
Estimating the value of R
Where:
It is recommended that whenever the control loop
compensation network is modified, f
for the correct frequency and if necessary, adjust R
Compensation Design
Figure 6 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C
integrated inside the IC, connecting across the FB pin and the
COMP signal. R
compensator. The frequency domain transfer function is given
by Equation 12:
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R
ISL6228 makes the LC output filter resemble a first order
system in which the closed loop stability can be achieved with
the recommended Type-II compensation network. Intersil
provides a PC-based tool (example page is shown later) that
can be used to calculate compensation network component
values and help simulate the loop frequency response.
f
R
G
SW
FSET
COMP
COMP
- f
- R
- K = 1.5 x 10
ISL6228
=
SW
FIGURE 6. COMPENSATION REFERENCE CIRCUIT
FSET
-------------------------- -
K R
C
=
s ( )
INT
⋅
is the PWM switching frequency
FSET
----------------- -
K f
1
FSET
=
•
= 100pF
is the f
REF
EA
1
SW
-------------------------------------------------------------------------------------------
s R
•
that is connected from the FSET pin to the
TOP
+
-
-10
1
TOP
SW
+
, R
FB
s R
•
•
FB
C
programming resistor
(
INT
, C
TOP
FSET
FB
•
(
R
11
1
+
BOTTOM
R
and C
+
INT
is written as Equation 11:
R
FB
SW
s R
FB
•
R
is a 100pF capacitor
) C
TOP
is programmed by the
SW
•
FB
INT
3
FB
•
modulator used in the
C
C
should be checked
form the Type-II
FB
FB
)
FSET
(EQ. 12)
(EQ. 10)
(EQ. 11)
VO
.
ISL6228
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 13:
The output inductor peak-to-peak ripple current is written as
Equation 14:
I
A typical step-down DC/DC converter will have an I
20% to 40% of the maximum DC output load current. The
value of I
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by Equation 15:
Where I
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance C
into which ripple current I
a corresponding ripple voltage V
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are written as
Equation 16:
and Equation 17:
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered. A capacitor
D
P
ΔV
ΔV
PP
COPPER
=
ESR
C
=
---------
V
V
=
IN
V
----------------------------- -
O
-----------------------------
8 C
O
LOAD
=
f
•
SW
PP
•
I
(
I
=
P-P
1 D
P-P
O
•
is selected based upon several criteria such as
–
I
•
L
LOAD
f
is the converter output DC current.
•
SW
E
)
SR
2
•
DCR
P-P
can flow. Current I
P-P
across C
P-P
O,
is achieved.
PP
which is the
August 27, 2007
develops
P-P
(EQ. 17)
(EQ. 13)
(EQ. 15)
(EQ. 16)
(EQ. 14)
FN9095.1
of
O