isl6620 Intersil Corporation, isl6620 Datasheet - Page 5

• Manufacturer Part Number: isl6620
• Description: Vr11.1, 4-phase Pwm Controller With Light Load Efficiency Enhancement And Load Current Monitoring
• Manufacturer: Intersil Corporation

Electrical Specifications
NOTE:
Functional Pin Description
LGATE Rise Time (Note 4)
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
Minimum Lgate on time at Diode emulation
OUTPUT (Note 4)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
4. Limits should be considered typical and are not production tested.
PACKAGE PIN #
SOIC
1
2
3
4
5
6
7
8
-
-
DFN
3, 8
10
11
1
2
4
5
6
7
9
PARAMETER
SYMBOL
PHASE
UGATE
LGATE
BOOT
PWM
GND
VCC
PAD
PIN
NC
EN
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal Bootstrap
Device” on page 7 for guidance in choosing the capacitor value.
No connect.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation.
See “Advanced PWM Protocol (Patent Pending)” on page 6 for further details. Connect this pin to the PWM output
of the controller.
Bias and reference ground. All signals are referenced to this node. It is also the power-ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect this pin to 5V bias supply. This pin supplies power to the upper gate and lower gate drive. Place a high
quality low ESR ceramic capacitor from this pin to GND.
Enable input pin. Connect this pin high to enable driver and low to disable driver.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
R_U_SOURCE 20mA source current
R_L_SOURCE 20mA source current
t_LG_ON_DM VCC = 5V
I_L_SOURCE
I_U_Source
R_U_SINK
R_L_SINK
I_U_SINK
SYMBOL
I_L_SINK
t_PDHU
t_PDHL
t_PDLU
t_PDLL
t_RL
t_FU
t_FL
ISL6620, ISL6620A
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, 10% to 90%
VCC = 5V, 3nF load, adaptive
VCC = 5V, 3nF load, adaptive
VCC = 5V, 3nF load
VCC = 5V, 3nF load
VCC = 5V, 3nF load
VCC = 5V, 3nF load
20mA sink current
VCC = 5V, 3nF load
VCC = 5V, 3nF load
20mA sink current
TEST CONDITIONS
FUNCTION
MIN
230
TYP
330
0.4
40
23
18
25
8
8
4
2
1
2
1
2
1
4
MAX
450
April 25, 2008
UNITS
FN6494.0
ns
ns
ns
ns
ns
ns
ns
ns
Ω
Ω
Ω
Ω
A
A
A
A