isl55210 Intersil Corporation, isl55210 Datasheet
isl55210
Available stocks
Related parts for isl55210
isl55210 Summary of contents
Page 1
... A companion device, the ISL55211, includes on-chip feedback and 3 possible gain setting connections where an internally fixed gain solution is preferred. The ISL55210 is available in a leadless TQFN package and is specified for operation over the -40ºC to +85ºC ambient temperature range. ...
Page 2
... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL55210. For more information on MSL please see techbrief TB363. 2 ...
Page 3
... Slew Rate (Differential) Differential Rise/Fall Time 2nd-order Harmonic Distortion 3rd-order Harmonic Distortion 2nd-order Intermodulation Distortion 3rd-order Intermodulation Distortion Input Voltage Noise Input Current Noise 3 ISL55210 Thermal Information (T = +25°C) A Thermal Resistance (Typical) +0.3V to GND-0. TQFN Package (Notes Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C Maximum Continuous Operating Junction Temperature .+135° ...
Page 4
... Gain Output Common-Mode Offset from CM Input CM Default Voltage CM Input Bias Current CM Input Voltage Range CM Input Impedance POWER SUPPLY Specified Operation Voltage Quiescent Current Power-supply Rejection (PSRR ISL55210 = +3.3V Test Conditions 12dB open (1.2V nominal) unless otherwise specified. CM CONDITIONS Differential T = +25° -40° ...
Page 5
... Input Bias Current Input Impedance Turn-on Time Delay Turn-off Time Delay NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. 7. Parameters denoted by an “*” are ATE tested. 5 ISL55210 = +3.3V Test Conditions 12dB open (1.2V nominal) unless otherwise specified. CM CONDITIONS Referenced to GND Assured on above 1 ...
Page 6
... TEST FREQUENCIES CENTER (MHz) FIGURE 4. IM2 AND IM3 vs GAIN 12 11 GAIN = 15dB 200 FREQUENCY (MHz) FIGURE 6. NOISE FIGURE 6 ISL55210 ≈ +25°C, unless otherwise noted 3.3V 15dB 15 21dB 12 9 33dB 6 TEST CIRCUIT # FIGURE 3 ...
Page 7
... FIGURE 10. HD2 AND HD3 vs GAIN -50 -60 HD2, 100Ω -70 HD2, 200Ω -80 HD3, 50Ω -90 HD2, 500Ω -100 -110 -120 20 FREQUENCY (MHz) FIGURE 12. HD2 AND HD3 ISL55210 ≈ +25°C, unless otherwise noted 3.3V -60 TEST CIRCUIT #1, R -70 -80 HD3 3V P-P -90 -100 -110 HD3 1V P-P ...
Page 8
... FREQUENCY (Hz) FIGURE 16. SMALL SIGNAL RESPONSE vs GAIN 200mV P -12 -15 -18 TEST CIRCUIT #3 COMMON MODE AC OUTPUT - FREQUENCY (MHz) FIGURE 18. V PIN INPUT FREQUENCY RESPONSE TO OUTPUT CM COMMON MODE 8 ISL55210 ≈ +25°C, unless otherwise noted 3.3V 10.0 1.7 1.6 1.5 PHASE 15dB 1.4 1.3 1.0 1.2 1.1 1.0 PHASE G = 21dB PHASE 0 27dB 0.8 ...
Page 9
... ENABLED PD DISABLED 2µs/DIV FIGURE 22. ENABLE/DISABLE TIMES 2.5 OUTPUT 2.0 1.5 1.0 INPUT 0.5 0 -0.5 -1.0 -1.5 -2.0 TEST CIRCUIT #1 -2 100 TIME (ns) FIGURE 24. OVERDRIVE RECOVERY 9 ISL55210 ≈ +25°C, unless otherwise noted 3.3V 1.5 1.0 0.5 0 -0.5 -1.0 TEST CIRCUIT #1, 50MHz SQUARE WAVE INPUT -1 TEST CIRCUIT # -10 -12 -14 -16 ...
Page 10
... V will also appear as the input common mode voltage. This provides a very easy way to control the ISL55210 I/O common mode operating voltages for an AC coupled signal path. The internal common mode loop holds the output pins to V ...
Page 11
... FIGURE 29. TEST CIRCUIT #2 4-PORT S-PARAMETER MEASUREMENTS Using this measurement allows the full small single bandwidth of the ISL55210 to be exposed. Many of the other measurements are using I/O transformers that are limiting the apparent bandwidth to reduced level. Figure 16 shows a series of normalized differential S21 curves for gains of 12dB to 30dB in 6dB steps. These are simply stepping two feedback resistor values (R 1600Ω ...
Page 12
... For single supply operation, the ground pins are at ground as is the exposed metal pad on the underside of the package. The ISL55210 can operate split supply where then the ground pins will ...
Page 13
... V control input voltage even during shutdown (or CM the default value). This is intended to hold the ISL55210 output near the desired common mode output level during shutdown. This improves turn on characteristic and keeps the output voltages in a safe range for downstream circuitry. ...
Page 14
... Driving ADCs Many of the intended applications for the ISL55210 are as a low power, very high dynamic range, last stage interface to high 25 performance ADCs. The lowest power ADCs, such as the 1µ ...
Page 15
... Here very high frequency interstage low pass filters can be provided. Again, the R reduce the IR drop from the V shows up on the output of the ISL55210, to the ADC input pins. In this case, split supplies are required to satisfy the amplifier output and input common mode range limits discussed earlier ...
Page 16
... Layout Considerations The ISL55210 pinout is organized to isolate signal I/O along one axis of the package with ground, power and control pins on the other axis. Ground and power should be planes coming into the upper and lower sides of the package (see the Pin Configuration on page 2). The signal I/O should be laid out as tight as possible ...
Page 17
... R0 DNP R7 0Ω R4 R23 50Ω R8 200Ω 0Ω R2 DNP Cterm2 2.2pF PD R22 50Ω FIGURE 38. SCHEMATIC FOR ISL55210, ISL55211 SINGLE INPUT TRANSFORMER EVM REV. C R21 VCC 200Ω/DNP C3 100nF C2 1k/DNP 100nF TP1 R17 R18 200Ω 50Ω TEST POINT C9 100nF 200Ω ...
Page 18
... Package Outline Drawing L16.3x3D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 3/10 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW (2.80 TYP) ( 1.60) TYPICAL RECOMMENDED LAND PATTERN 18 ISL55210 4X 1.50 A 12X 0. 16X 0.40±0.10 BOTTOM VIEW 0.75 ±0.05 SIDE VIEW (12X 0.50) (16X 0.23 REF C (16X 0.60) DETAIL "X" ...