isl33001 Intersil Corporation, isl33001 Datasheet

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isl33001

Manufacturer Part Number
isl33001
Description
2-wire Bus Buffer With Rise Time Accelerators And Hot Swap Capability
Manufacturer
Intersil Corporation
Datasheet

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2-Wire Bus Buffer With Rise Time Accelerators and
Hot Swap Capability
ISL33001, ISL33002, ISL33003
The ISL33001, ISL33002, ISL33003 2-Channel Bus
Buffers provide the necessary buffering for extending the
bus capacitance beyond the 400pF maximum specified
by the I
ISL33002, ISL33003 feature rise time accelerator
circuitry to reduce power consumption from passive bus
pull-up resistors and improve data-rate performance. All
devices also include hot swap circuitry to prevent
corruption of the data and clock lines when I
are plugged into a live backplane and level translation for
mixed supply voltage applications.
The ISL33001, ISL33002, ISL33003 operates at supply
voltages from +2.3V to +5.5V at a temperature range of
-40°C to +85°C.
Summary of Features
Related Literature*
• AN1543, “ISL33001EVAL1Z, ISL33002EVAL1Z,
Typical Operating Circuit
ISL33001
ISL33002
ISL33003
NUMBER
March 18, 2010
FN7560.0
ISL33003EVAL1Z Evaluation Board Manual”
PART
µC
SDA
SCL
EN
2
V
C specification. In addition, the ISL33001,
TRANSLATION
CC1
LEVEL
Yes
Yes
No
+3.3V
ISL33003
+5.0V
ENABLE
1
PIN
Yes
Yes
No
V
READY
(see page 14)
CC2
PIN
Yes
No
No
PLANE
BACK
1-888-INTERSIL or 1-888-468-3774
GND
SDA
SCL
ACCELERATOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
2
DISABLE
C devices
Yes
No
No
DEVICE
DEVICE
I
I
2
2
A
B
C
C
Features
• 2 Channel I
• +2.3VDC to +5.5VDC Supply Range
• >400kHz Operation
• Bus Capacitance Buffering
• Rise Time Accelerators
• Hot-Swapping Capability
• ±6kV Class 3 HBM ESD Protection On All Pins
• ±12kV HBM ESD Protection on SDA/SCL Pins
• Enable Pin (ISL33001 and ISL33003)
• Logic Level Translation (ISL33002 and ISL33003)
• READY Logic Pin (ISL33001)
• Accelerator Disable Pin (ISL33002)
• Pb-Free (RoHS Compliant) 8 Ld TDFN (3mmx3mm)
• Low Quiescent Current . . . . . . . . . . . . . 2.2mA typ
• Low Shutdown Current . . . . . . . . . . . . . . 0.5µA typ
Applications*
• I
• Server Racks for Telecom, Datacom, and Computer
• Desktop Computers
• Hot-Swap Board Insertion and Bus Isolation
Bus Accelerator Performance
and 8 Ld MSOP packages
Servers
All other trademarks mentioned are the property of their respective owners.
2
C Bus Extender and Capacitance Buffering
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
100kHz I
2
Copyright Intersil Americas Inc. 2010. All Rights Reserved
C Compatible Bi-Directional Buffer
AND 400pF BUS CAPACITANCE
2
C BUS WITH 2.7kΩ PULL-UP RESISTOR
WITHOUT BUFFER
WITH BUFFER
TIME (2µs/DIV)
(see page 14)

Related parts for isl33001

isl33001 Summary of contents

Page 1

... I are plugged into a live backplane and level translation for mixed supply voltage applications. The ISL33001, ISL33002, ISL33003 operates at supply voltages from +2.3V to +5. temperature range of -40°C to +85°C. Summary of Features ...

Page 2

... For Moisture Sensitivity Level (MSL), please see device information page for information on MSL please see techbrief TB363. Pin Configurations ISL33001 (8 LD TDFN) TOP VIEW EN 1 SCL_OUT SCL_IN GND 4 2 ISL33001, ISL33002, ISL33003 TEMP. RANGE (°C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 - CC1 ...

Page 3

... NOTES NUMBER V CC1 V ISL33002, CC2 ISL33003 GND EN ISL33001 ISL33003 READY ISL33001 only ACC ISL33002 only SDA_IN SDA_OUT SCL_IN SCL_OUT PD Thermal Pad; TDFN only 3 ISL33001, ISL33002, ISL33003 (Continued CC1 SCL_OUT SDA_OUT 7 6 SDA_IN 5 ACC V 8 CC1 SDA_OUT 7 SCL_OUT SDA_IN PIN 8 V power supply, +2 ...

Page 4

... Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersi.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range and V CC1 = +2.3V to +5.5V CC1 CC1 CC2 CONDITIONS ISL33002 and ISL33003 V = 5.5V; ISL33001 only (Note 11) CC1 5.5V; ISL33002 and CC1 CC2 ISL33003 (Note 11 5.5V; ISL33002 and CC2 CC ISL33003 (Note 11 5.5V GND; ISL33001 ...

Page 5

... Current TIMING CHARACTERISTICS SCL/SDA Propagation t PHL Delay High to Low 5 ISL33001, ISL33002, ISL33003 = +2.3V to +5.5V CC1 CC1 CC2 CONDITIONS ISL33001 and ISL33003 (Figure 1) (Figure 2, Note 12) ISL33001 only ISL33001 only (Note 10) ISL33001 only (Note 10 +2.5V 3mA; CC1 PULLUP ISL33001 only V = 2.7V 2.7V; CC1 CC2 (ACC = 0 ...

Page 6

... SCL pins 3.3V; CC1 V = 3.3V, ISL33002 and ISL33003 CC2 (Figure SDA_IN Logic High for t > Enable Delay, t prior to SCL_IN transition - Bus Idle Time Measured on ISL33001 only - ISL33002 and ISL33003 performance inferred from ISL33001 10kΩ 10kΩ ...

Page 7

... FIGURE 5A. TEST CIRCUIT I = CΔV/Δt ACC V 2.7kΩ 100kΩ V SCL_OUT SCL_IN GND 2nF FIGURE 6. ACCELERATOR CURRENT TEST CIRCUIT 7 ISL33001, ISL33002, ISL33003 (Continued) 900Ω 900Ω SDA_OUT SCL_OUT SDA_IN 0V SDA_OUT FIGURE 4. OUTPUT LOW VOLTAGE SCL_IN OR 2.7kΩ 2.7kΩ SDA_OUT SCL_OUT OR ...

Page 8

... A valid connection state is either a BUS IDLE condition (see Figure STOP BIT condition (a rising edge on SDA_IN when SCL_IN is high) along with the SCL_OUT and SDA_OUT pins being logic high. Note - For the ISL33001 and ISL33003 with EN pins, after coming out of UVLO, there will be an additional SDA_OUT M2 ...

Page 9

... IC is hot plugged into a live back plane that may have the bus communicating with other devices. Note - For ISL33001 and ISL33003 with EN pins, the pre-charge circuitry is active only after coming out of UVLO and having the device enabled. Connection Circuitry ...

Page 10

... For a bus that is operating normally without active rise time circuitry, using the ISL33001, ISL33002, ISL33003 buffer will allow larger pull-up resistor values to reduce sink currents when the bus is driving low. ...

Page 11

... (mA) OL FIGURE 15. SDA/SCL OUTPUT LOW VOLTAGE vs SINK CURRENT ISL33001, ISL33002, ISL33003 10pF OUT Specified. (Continued -40°C 4.5 5.0 5.5 6.0 FIGURE 12. I CC1 +25° 4.5 5.0 5.5 6.0 FIGURE 14. I CC2 ...

Page 12

... CC FIGURE 19. ACCELERATOR PULL-UP CURRENT +85° +25° -40° 2.0 2.5 3.0 3.5 4.0 V (V) CC FIGURE 21. PROPAGATION DELAY H ISL33001, ISL33002, ISL33003 10pF OUT Specified. (Continued) 100 FIGURE 18. INPUT TO OUTPUT OFFSET VOLTAGE vs 800 700 600 500 400 ...

Page 13

... Typical Performance Curves FIGURE 23. SDA/SCL PIN CAPACITANCE vs TEMPERATURE vs V Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): GND PROCESS: 0.25µm CMOS 13 ISL33001, ISL33002, ISL33003 10pF OUT Specified. (Continued 2. 3. -30 - TEMPERATURE (°C) ...

Page 14

... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 14 ISL33001, ISL33002, ISL33003 for a complete list of Intersil product families. ISL33001, ISL33002, ISL33003 www.intersil.com/askourstaff http://rel.intersil.com/reports/search.php www.intersil.com/product_tree www.intersil.com/design/quality CHANGE www ...

Page 15

... LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) Rev 0, 2/08 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 2. . TYPICAL RECOMMENDED LAND PATTERN 15 ISL33001, ISL33002, ISL33003 A PIN #1 INDEX AREA 6 B 3.00 0 .80 MAX ( 1. 0. 0.25 ) NOTES: 1. Dimensions are in millimeters. Dimensions Dimensioning and tolerancing conform to AMSE Y14.5m-1994. ...

Page 16

... LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW 2X 1.950 PIN #1 1 INDEX AREA 0.30 ± 0.10 2.30 ±0.10 BOTTOM VIEW 16 ISL33001, ISL33002, ISL33003 A B (1.50) ( 2.90 ) PIN 1 6X 0.65 0.75 ±0.05 1.50 ±0. 0.30 ±0.05 0. NOTES: 1. Dimensions are in millimeters. Dimensions ...

Page 17

... M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/10 3.0±0. PIN TOP VIEW H 0.25 - 0.036 0. A-B D SIDE VIEW 1 (5.80) (4.40) (3.00) (0.65) TYPICAL RECOMMENDED LAND PATTERN 17 ISL33001, ISL33002, ISL33003 5 D 1.10 MAX 4.9±0.15 3.0±0.05 5 0.65 BSC 0.85±010 C SEATING PLANE 0.10 C 0.10 ± 0.05 NOTES (0.40) (1.40 SIDE VIEW 2 ...

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