isl3873 Intersil Corporation, isl3873 Datasheet - Page 25

• Manufacturer Part Number: isl3873
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor
• Manufacturer: Intersil Corporation

Meanwhile signal quality and signal frequency
measurements are made simultaneous with symbol timing
measurements. A CS1 followed by SQ1 active, or two
consecutive SQ1s will cause the part to finish the acquisition
phase and enter the tracking phase.
Prior to initial acquisition the NCO is inactive (0Hz) and
carrier phase measurement are done on a symbol by symbol
basis. After acquisition, coherent DPSK demodulation is in
effect. After a brief setup time as illustrated on the timeline,
the signal begins to emerge from the demodulator.
POWER
RAMP
TX_AGC_IN
TX_IF_AGC
TX
ANTSEL
ANTSEL
I
V
2
REF
REF
AND INITIAL DETECTION
AGC SETTLE AND LOCK
20 SYMBOLS
6-BIT
V
25
6-BIT
DAC
ADC
DDA
FIGURE 17. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
(ANALOG)
TX_PE
GENERATOR
FIGURE 16. ACQUISITION TIMELINE, NON DIVERSITY
TIMING
MCLK
REGISTER
CONTROL
VERIFY AND CIR/FREQUENCY
ESTIMATION AND CMF/NCO
TX AGC
MCLK
56 SYMBOL SYNC
GND (ANALOG)
20 SYMBOLS
JAMMING
ISL3873
BARKER/CCK
MODULATOR,
TRANSMIT
FILTER
START SFD SEARCH
CONTROL
DESCRAMBLER
It takes 7 more symbols to seed the descrambler before valid
data is available. This occurs in time for the SFD to be received.
At this time the demodulator is tracking and in the coherent
PSK demodulation mode so it will no longer acquire new
signals. If a much larger signal overrides the signal being
demodulated (a collision), the demodulator will abort the
tracking process and attempt to acquire the new signal. Failure
to find an SFD within the SFD timeout interval will result in a
receiver reset and return to acquisition mode.
STATE
V
TX
DD
SEED
7 SYM
(DIGITAL)
PREAMBLE/HEADER
SCRAMBLER
GENERATOR
TX_DATA
CRC-16
GND (DIGITAL)
INTERNAL
SIGNALS
16 SYMBOLS
DAC
DAC
MAC
CONTROL
SIGNALS
TX_RDY
RXCLK
TXCLK
SFD
CCA
TXD
START DATA
SFD DET
TXI+/-
TXQ+/-