dt28f016sv080 Intel Corporation, dt28f016sv080 Datasheet - Page 40
dt28f016sv080
Manufacturer Part Number
dt28f016sv080
Description
16-mbit 1 Mbit X 16, 2 Mbit X 8 Flashfile Memory
Manufacturer
Intel Corporation
Datasheet
1.DT28F016SV080.pdf
(63 pages)
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28F016SV FlashFile™ MEMORY
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8.
2. OE# may be delayed up to t
3. Sampled, not 100% tested. Guaranteed by design
4. This timing parameter is used to latch the correct BSR data onto the outputs.
5. Device speeds are defined as:
6. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
7. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
8. CE
9.
10. Page Buffer Reads only.
40
The address setup requirement for Extended Status Register reads must only be met referenced to the falling edge of the
last control signal to become active (CE
an Extended Status Register read, specification t
activated after OE#, specification t
X
# is defined as the latter of CE
65/70 ns at V
75 ns at V
70/80 ns at V
120 ns at V
CC
CC
CC
CC
= 3.3V
= 3.3V
= 5V equivalent to
= 5V equivalent to
ELQV
-t
GLQV
0
AVEL
# or CE
after the falling edge of CE#, without impacting t
must be referenced.
0
#, CE
1
# going low, or the first of CE
1
# or OE#). For example, if CE
AVGL
must be met. On the other hand, if either CE
0
# or CE
0
# and CE
1
# going high.
ELQV
1
# are activated prior to OE# for
.
0
# or CE
E
1
# (or both) are
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