fm3316 Ramtron Corporation, fm3316 Datasheet - Page 5

• Manufacturer Part Number: fm3316
• Description: 3v Integrated Processor Companion With Memory
• Manufacturer: Ramtron Corporation

60 ms increments via a 5-bit nonvolatile setting
(register 0Ch).
The watchdog also incorporates a window timer
feature that allows a delayed start. The starting time
and ending time defines the window and each may be
set independently.
resolution and 0 ms to 775 ms range.
The watchdog EndTime value is located in register
0Ch, bits 4-0, the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 0Ah. Writing the correct
pattern will also cause the timer to load new timeout
values. Writing other patterns to this address will not
affect its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
timer as described above. This assures that the full
timeout is provided immediately after enabling. The
watchdog is disabled when V
Note setting the EndTime timeout setting to all
zeroes (00000b) disables the timer to save power.
The listing below summarizes the watchdog bits.
Watchdog StartTime
Watchdog EndTime
Watchdog Enable
Watchdog Restart
Watchdog Flags
The programmed StartTime value is a guaranteed
maximum time while the EndTime value is a
guaranteed minimum time, and both vary with
temperature and V
additional controls associated with its operation. The
nonvolatile enable bit WDE allows the /RST to go
Rev. 1.1
Dec. 2007
Watchdog
Timebase
Restart
RST
100 ms
Figure 3. Watchdog Timer
clock
Figure 4. Window Timer
Start
Time
DD
Window
Timer Settings
Down Counter
The starting time has 25 ms
voltage. The watchdog has two
Watchdog
WDST4-0 0Bh, bits 4-0
WDET4-0 0Ch, bits 4-0
WDE
WR3-0
EWDF,
LWDF
WR3-0 = 1010b
DD
End
Time
drops below V
0Ch, bit 7
0Ah, bits 3-0
09h, bit 7
09h, bit 6
100 ms (max)
WDE
to restart
/RST
TP
.
active if the watchdog reaches the timeout without
being restarted. If a reset occurs, the timer will restart
on the rising edge of the reset pulse. If WDE is not
enabled, the watchdog timer still runs but has no
effect on /RST. The second control is a nibble that
restarts the timer, thus preventing a reset. The timer
should be restarted after changing the timeout value.
This procedure must be followed to properly load the
watchdog registers:
The restart command in step 3 must be issued before
t
timer starts counting when the restart command is
issued.
Manual Reset
The /RST is a bi-directional signal allowing the
FM33xx to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms (max.). This effectively filters and de-
bounces a reset switch. After this timeout (t
user may continue pulling down on the /RST pin, but
SPI commands will not be locked out.
Note the internal weak pull-up eliminates the need
for additional external components.
Reset Flags
In case of a reset condition, a flag bit will be set to
indicate the source of the reset. A low-V
indicated by the POR bit, register 09h bit 5. There are
two watchdog reset flags - one for an early fault
(EWDF) and the other for a late fault (LWDF),
located in register 09h bits 7 and 6. A manual reset
will result in no flag being set, so the absence of a
flag is a manual reset. Note that the bits are set in
response to reset sources but they must be cleared by
the user. It is possible to read the register and have
DOG2
1.
2.
3.
, which was programmed in step 2. The window
FM33256/FM3316 SPI Companion w/ FRAM
Behavior
Switch
RST
MCU
Write the StartTime value
Write the EndTime value and WDE=1 0Ch
Issue a Restart command
Switch
Reset
Figure 5. Manual Reset
FM33xx
drives
RST
100 ms (max.)
FM33xx
DD
Page 5 of 28
Address
0Bh
0Ah
RPW
reset is
), the