fm3808 Ramtron Corporation, fm3808 Datasheet - Page 12

• Manufacturer Part Number: fm3808
• Description: 256kb Bytewide Fram W/ Real-time Clock
• Manufacturer: Ramtron Corporation

Power Monitor
The FM3808 provides a power management scheme
with either power-fail interrupt or processor-reset
capability. It also controls the internal switch to
backup power for the timekeeper and protects the
memory from low-V
based on an internal band-gap reference circuit that
compares the V
The power monitor compares V
The first is an interrupt threshold (V
drops below the V
power fail flag PF (7FF0h bit D5). It also can drive
the INT pin as described in the Interrupts section.
The second threshold is the low V
voltage V
the FRAM array, which may otherwise result in
corrupted data. At this point, access to the memory
array and clock registers will be blocked until V
rises above V
below V
will be ignored. On power up, the chip enable input
will be ignored while V
pulled high prior to V
At the third threshold, the internal supply switches
from V
switchover will occur at the level when V
than V
begin to draw power from V
event may be above or below the V
depending on the battery voltage.
Rev. 1.3 (EOL)
Feb. 2006
BAK
DD
TP
LO
. When switchover occurs, the clock will
. When V
. This level prevents low voltage writes to
to V
LO
DD
. The lockout voltage V
voltage to various thresholds.
BAK
TP
DD
DD
DD
level, the event will set the
access. The power monitor is
DD
reaching V
drops below V
for the timekeeper. This
is below V
BAK
DD
rather than V
DD
to three thresholds.
LO
memory lockout
.
TP
TP
LO
LO
). When V
LO
, but must be
or V
always trips
, all inputs
DD
DD
LO
is less
. This
level
DD
DD
To conserve the life of the backup source, the power
monitor circuit is only operated from V
has dropped too low for the monitor to work, it ceases
operation.
reenergize as V
after the band-gap energizes, the reverse sequence
will occur. As soon as the band gap is functional, it
will re-assert both selections for switch over and
power fail. As the V
revert to the primary power source V
memory access and clock operation. As the V
above V
Note that the PF flag will not be cleared until the
Flags/Control register is read.
The following figure illustrates the various events
tracked by the power monitor.
In the diagram, V
low interrupt will have sufficient drive strength to
pull the INT pin low.
V
DD
V
V
TP
V
LO
BAK
V
TP
RST
Figure 4. Power Monitor Events
, the power-fail condition will be removed.
However,
DD
RST
rises on power up. On power-up,
is the voltage at which an active-
DD
rises further, the device will
the
power
DD
monitor
DD
. When V
V
Page 12 of 27
, allowing
RST
FM3808
V
V
DD
BAK
V
LO
TP
rises
will
DD