16t202da1j Pacer Components, 16t202da1j Datasheet
16t202da1j
Related parts for 16t202da1j
16t202da1j Summary of contents
Page 1
... CYC - t (/RD) =70ns 100ns WH - Topr:(-20 ~ +75) (- Tstg:(-40 ~ +85) (-50 ~ +85 :100ms(Min.) 1ms(Min.) OFF - t :1ms(Max.) 1us(Min.) r SSVD) in Section-1 (SCOPE) Page - Rev. 4.0 Model No.: 16T202DA1J Remark All Pages Page - 5 Page - 4 Page - 8 Page - 5 Page - 7 Page - 8 Page - 2 Page - 3 Page - 17 All Pages Customer’s Approval ...
Page 2
... Set CG-RAM Address. ....................................................................................................................................... 6.2.8 Set DD-RAM Address. ....................................................................................... 6.2.9 Read Busy Flag and Address. 6.2.10 Write Data DD-RAM. 6.2.11 Read Data from CG or DD-RAM.............................................................................................................. Page - 16 6.3 Example of Initialization after Power ON * Character Code Table (CG-RAM & CG-ROM). 16T202DA1J (Rev. 4.0) ........................................................................................ ......................................................................................................................... ................................................................................................ ............................................................................................................... .............................................................................................................. ................................................................................................................. ................................................................................................................ ............................................................................................................................ ...
Page 3
... LCD Compatible VFD Module 1. SCOPE * This specification applies to VFD module (Model No.:16T202DA1J) manufactured by Samsung SDI or SSVD. 2. FEATURES * LCD Compatible: Drop-in-replacement (Same Interface and Mechanical Dimension as LCD Module). * High Quality, Attractive and Readable Display: 5*7 Dot Matrix Type Vacuum Fluorescent Display. ...
Page 4
... Input Current (V "L" level Input Current (V Luminance *1) The in-rush current can be approx. 5 times the specified supply current at power on. *2) A 10k Ohm resistance is pulled-up on each input signals for TTL compatibility. 16T202DA1J (Rev. 4. Dot Matrix with Cursor Symbol ...
Page 5
... SU 20ns/Min. R DB0~DB7 Fig.-2. Data Write-in Timing for M68 Interface Mode R/W t (RS,/R/W) SU 20ns/Min DB0~DB7 Fig.-3. Data Read-out Timing for M68 Interface Mode 16T202DA1J (Rev. 4.0) t (VCC) r 1us/Min. t (*) WAIT 100us/Min. 500ns/Min. Fig.-1. Power-on Reset and /RST Signal Timing t (RS,R/W) H 10ns/Min. t (E) CYC 500ns/Min ...
Page 6
... VCC - 3 /RST (*) Input 4 RS Input 5 R/W (/WR) Input 6 E (/RD) Input 7 DB0 8 DB1 9 DB2 10 DB3 I/O 11 DB4 12 DB5 13 DB6 14 DB7 16T202DA1J (Rev. 4.0) t (/WR) CYC 200ns/Min. t (RS) H 10ns/Min. t (/WR) WL 30ns/Min. t (/WR) WH 100ns/Min. t (DATA) t (DATA 30ns/Min. 10ns/Min. Valid Data Input t (/WR) CYC 200ns/Min. t (RS) H 10ns/Min ...
Page 7
... R JP1 /RST #3 Jumper Switch for External Reset Rup*8 (10kOhm) DB0~DB7 8 #7~ GND #1 4.10 Connector through Hole Location 16T202DA1J (Rev. 4.0) 72 VDD1 A1~A72 20 G1~G20 E(/RD) R/W(/WR) RS VFD /RST Controller VSS MPU Jumper Switch to Select Interfacing Mode D0~D7 VDD2 DC/DC Converter Fig.-6 System Block Diagram #14 #13 ...
Page 8
... LCD Compatible VFD Module 4.11 Outer Dimensions 4.12 Pattern Details 16T202DA1J (Rev. 4.0) Unit: mm Tolerance unless otherwise specified: * Mounting Hole Size: +/- 0.3 * Length: Fig.-8 Outer Dimensions Fig.-9 Pattern Details Page - Range < 10: +/- 0.5 Range > 10: +/- 1.0 ...
Page 9
... Character Generator RAM (CG-RAM) The CG-RAM stores the pixel information (1 = pixel on pixel off) for the eight user-definable 5*7 characters including cursor. Valid CG-RAM addresses are 00H to 3FH. CG-RAM not being used to define characters can be used as general purpose RAM (lower 5 16T202DA1J (Rev. 4.0) i80 / write as an internal operation (display clear, etc ...
Page 10
... DB7) are transferred before the four low order bits (for 8-bit operation, DB0 to DB3). The busy flag (BF) are performed before transferring the higher 4 bits. BF checks are not required before transferring the lower 4 bits. For 8-bit interface data, all eight bus lines (DB0 to DB7) are used. 16T202DA1J (Rev. 4.0) CG-RAM Address CG-RAM Data Hex ...
Page 11
... External Reset When the "JP1" is opened, this function is not effective. Therefore user want to use external H/W reset function (pin #3, /RST), then you must close the soldering switch "JP1". The required pulse width of /RST signal must be longer than 500ns. 16T202DA1J (Rev. 4.0) BF ...
Page 12
... Data RAM * Display Shift Enabled * CG-RAM: Character * Cursor Shift Enabled Generator RAM * ACG: CG-RAM * S Display Shift Address * S Cursor Move * ADD: DD-RAM Address * R Shift to the Right * ACC: Address Counter * R Shift to the Left 16T202DA1J (Rev. 4.0) Instruction Code ...
Page 13
... Cursor moves one character to the left 1 0 Cursor moves one character to the right 0 1 Display shifts one character to the right without cursor Cursor moves one character to the left 1 1 Display shifts one character to the left without cursor 16T202DA1J (Rev. 4.0) DB3 DB2 DB1 DB0 Hex. Range ...
Page 14
... Select 1 line display (Using anode output A1 to A40. A41 to A80 fixed Low level.) BR1, BR0 flag controls the brightness of VFD by modulating pulse width of Anode output as follows. * BR0, BR1 = (0, 0): Brightness = 100% (0, 1): Brightness = 75% (1, 0): Brightness = 50% (1, 1): Brightness = 25% 16T202DA1J (Rev. 4.0) DB3 DB2 DB1 DB0 0 1 ...
Page 15
... DD-RAM is determined by the previous specification of the CG-RAM or DD-RAM address setting. After a write, the address is automatically increased or decreased by 1 according to the entry mode. The entry mode also determines the display shift. When data is written to the CG-RAM, the DB7, DB6 and DB5 bits are not displayed as characters. 16T202DA1J (Rev. 4.0) DB3 DB2 ...
Page 16
... Note) “Dn” is the binary data to be written-in. Power ON Function Set Display ON/OFF 16T202DA1J (Rev. 4.0) DB3 DB2 DB1 DB0 00H ~ 0FH for CG-RAM Code 10H ~ FFH for CG-ROM Code Wait for 100 us after Power ON Function set: - Data length: 8 bits ...
Page 17
... CG-RAM . (# CG-RAM . . (# CG-RAM . . (# 16T202DA1J (Rev. 4. ...