t5743n ATMEL Corporation, t5743n Datasheet - Page 11

• Manufacturer Part Number: t5743n
• Description: Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Duration of the Bit Check
If no transmitter signal is present during the bit check, the
output of the ASK/ FSK demodulator delivers random
signals. The bit check is a statistical process and T
varies for each check. Therefore, an average value for
T
T
T
T
ling mode.
In the presence of a valid transmitter signal, T
dependent on the frequency of that signal, f
count of the checked bits, N
Rev. A1, 25-May-00
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit–check–
counter
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit–check–
counter
( Lim_min = 14, Lim_max = 24 )
IC_ACTIVE
Bit check
Dem_out
Bit–check–
counter
Bit-check
Bit-check
Clk
Bit-check
. A higher baud-rate range causes a lower value for
depends on the selected baud-rate range and on
resulting in a lower current consumption in pol-
is given in the electrical characteristics.
Start–up mode
Start–up mode
Start–up mode
T
T
T
Start–up
Start–up
Start–up
0
0
0
Figure 15. Timing diagram for failed bit check (condition: CV_Lim >= Lim_max)
Figure 14. Timing diagram for failed bit check (condition: CV_Lim < Lim_min)
Bit-check
1
1
1
2 3 4 5 6
2 3 4 5 6
2 3 4 5 6
. A higher value for
Preliminary Information
Figure 13. Timing diagram during bit check
T
7 8 1
1
7
XClk
Bit–check mode
2
1
Sig
2
3
T
Bit-check
Bit–check
4 5
2
3
, and the
Bit-check
3
4 5
Bit–check mode
1/2 Bit
4 5
6 7 8 9
T
6 7 8 9
Bit–check
is
6 7 8 9
Bit check failed ( CV_Lim < Lim_min )
1/2 Bit
10
N
requiring a higher value for the transmitter pre-burst
T
Receiving Mode
If the bit check was successful for all bits specified by
N
cording to figure 11, the internal data signal is switched
to Pin DATA in that case and the data clock is available
after the start bit has been detected (figure 22). A con-
nected µC can be woken up by the negative edge at Pin
DATA or by the data clock at Pin DATA_CLK. The re-
ceiver stays in that condition until it is switched back to
polling mode explicitly.
10
11 12
Preburst
1/2 Bit
Bit-check
Bit-check
10
11 12
Bit–check mode
11 12 13 14
13 14 15 16 17 18 19
T
Bit–check
.
, the receiver switches to receiving mode. Ac-
thereby results in a longer period for T
15 16 17 18 1 2 3 4 5 6
Bit check ok
Sleep mode
0
T
Bit check failed ( CV_Lim >= Lim_max )
Sleep
20
21 22 23 24
7 8 9 10 11 12 13 14 15 1 2 3 4
1/2 Bit
T5743N
Sleep mode
T
0
Sleep
Bit check ok
11 (34)
Bit-check
1/2 Bit