st2024c Sitronix Technology Corporation, st2024c Datasheet - Page 10

• Manufacturer Part Number: st2024c
• Description: 24k 8-bit Single Chip Microcontroller
• Manufacturer: Sitronix Technology Corporation

9
9.2
RESET
A positive transition of RESET pin will then cause an
initialization sequence to begin. After the system has been
operating, a high on this line of a least two clock cycles will
cease ST2024C activity. When a positive edge is detected,
there is an initialization sequence lasting six clock cycles.
Then the interrupt mask flag is set, the decimal mode is
cleared and the program counter will loaded with the restart
vector from locations $FFFC (low byte) and $FFFD (high
byte). This is the start location for program control. This input
should be low in normal operation.
INTX interrupt
The IRX (INTX interrupt request) flag will be set while INTX
edge signal occurs. The INTX interrupt will be active once
IEX (INTX interrupt enable) is set, and interrupt mask flag is
cleared. Hardware will push ‘PC’, ‘P’ Register to stack and
set interrupt mask flag (I). Program counter will be loaded
with the INTX vector from locations $FFF8 and $FFF9.
DAC interrupt
The IRDAC (DAC interrupt request) flag will be set while
reload signal of DAC occurs. Then the DAC interrupt will be
executed when IEDAC (DAC interrupt enable) is set, and
interrupt mask flag is cleared. Hardware will push ‘PC’, ‘P’
Register to stack and set interrupt mask flag (I). Program
counter will be loaded with the DAC vector from locations
$FFF6 and $FFF7.
Ver 2.2
9
.
.
I
I
N
N
RESET
Name
Name
Name
Name
INTX
DAC
T
T
PT
BT
T1
Interrupt description
-
-
-
E
E
R
R
R
R
U
U
P
INT/EXT
P
External
External
External
Internal
Internal
Signal
Signal
Signal
Signal
T
T
-
-
-
S
S
TABLE 9-3: PREDEFINED VECTORS FOR INTERRUPT
Vector address
Vector address
Vector address
Vector address
$FFFD,$FFFC
$FFFB,$FFFA
$FFEF,$FFEE
$FFFF,$FFFE
$FFF9,$FFF8
$FFF7,$FFF6
$FFF5,$FFF4
$FFF3,$FFF2
$FFF1,$FFF0
10/54
Priority
T1 interrupt
The IRT1 (TIMER1 interrupt request) flag will be set while T1
overflows. With IET1 (TIMER1 interrupt enable) being set,
the T1 interrupt will executed, and interrupt mask flag will be
cleared. Hardware will push ‘PC’, ‘P’ Register to stack and
set interrupt mask flag (I). Program counter will be loaded
with the T1 vector from locations $FFF2 and $FFF3.
PT interrupt
The IRPT (Port-A interrupt request) flag will be set while
Port-A transition signal occurs. With IEPT (PT interrupt
enable)being set, the PT interrupt will be execute, and
interrupt mask flag will be cleared. Hardware will push ‘PC’,
‘P’ Register to stack and set interrupt mask flag (I). program
counter will be loaded with the PT vector from locations
$FFF0 and $FFF1.
BT interrupt
The IRBT (Base timer interrupt request) flag will be set when
Base Timer overflows. The BT interrupt will be executed
once the IEBT (BT interrupt enable) is set and the interrupt
mask flag is cleared. Hardware will push ‘PC’, ‘P’ Register
to stack and set interrupt mask flag (I). Program counter will
be loaded with the BT vector from locations $FFEE and
$FFEF.
1
2
3
4
5
6
-
-
-
Reserved
RESET vector
Reserved
PA0 edge interrupt
Reload DAC data interrupt
Reserved
Timer1 interrupt
Port-A transition interrupt
Base Timer interrupt
Comment
Comment
Comment
Comment
ST2024C
1/31/08