sc202amltrt Semtech Corporation, sc202amltrt Datasheet - Page 16

• Manufacturer Part Number: sc202amltrt
• Description: 3.5mhz, 500ma Step-down Regulator With Integrated Inductor And Digital Programmable Output
• Manufacturer: Semtech Corporation

Applications Information (continued)
calculating the minimum value required for C
following equation.
The input voltage ripple is at maximum level when the
input voltage is twice the output voltage (50% duty cycle
scenario).
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the PMOS switch.
Low ESR/ESL X5R ceramic capacitors are recommended
for this function. To minimize stray inductance, the capaci-
tor should be placed as close as possible to the IN and
GND pins. Table 3 lists recommended input capacitor
options from different manufacturers.
PCB Layout Considerations
The layout diagram in Figure 3 shows a recommended
PCB top-layer for the SC202A and supporting compo-
nents. Specified layout rules must be followed since the
layout is critical for achieving the performance specified in
the Electrical Characteristics table. Poor layout can
degrade the performance of the DC-DC converter and can
contribute to EMI problems, ground bounce, and resistive
voltage losses. Poor regulation and instability can also
result.
Manufacturer
Part Nunber
Murata
GRM188R60J475K
Murata
GRM188R60J106K
Taiyo Yuden
JMK107BJ475KA
TDK
C1608X5R0J475KT
C
IN
Table 3 — Recommended Input Capacitors
V
V
OUT
I
IN
OUT
V
1
ESR
V
V
OUT
IN
4.7±10%
4.7±10%
4.7±10%
10±10%
f
Value
(μF)
Type
X5R
X5R
X5R
X5R
Voltage
Rated
(VDC)
6.3
6.3
6.3
6.3
IN
LxWxH (mm)
Dimensions
1.6x0.8x0.8
1.6x0.8x0.8
1.6x0.8x0.8
1.6x0.8x0.8
Case Size
using the
0603
0603
0603
0603
The following guidelines are recommended for designing
a PCB layout:
1.
2.
3.
4.
5.
6.
3.5mm
C
as possible. This capacitor provides a low impedance
loop for the pulsed currents present at the buck
converter’s input. Use short wide traces to minimize
trace impedance. This will also minimize EMI and
input voltage ripple by localizing the high frequency
current pulses.
C
OUT pin.
Use a ground plane referenced to the GND pin. Use
several vias to connect to the component side ground
to further reduce noise and interference on sensitive
circuit nodes.
Route the output voltage feedback/sense trace
(connected to the SNS pin) away from the LX node
as shown in Figure 3 to minimize noise and magnetic
interference.
Minimize the resistance from the OUT and GND pins
to the load. This will reduce errors in DC regulation
due to voltage drops in the traces.
The two smaller exposed pads on this package should
not be connected to any traces. The area beneath
these two pads must be kept clear so that they do
not make electrical contact with any traces, including
ground.
IN
OUT
should be placed as close to the IN and GND pins
should be connected as closely as possible to the
IN
Figure 3 — Recommended PCB Layout
C
C
OUT
IN
OUT
GND
These pads should not
connected to the PCB.
be electrically
3.8mm
SC202A
LX
(no
connection
needed)
SC202A
SNS
CTL2
CTL1
CTL0
CTL3
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