82c881 ETC-unknow, 82c881 Datasheet
82c881
Related parts for 82c881
82c881 Summary of contents
Page 1
... FireLink 1394 OHCI Link Controller 82C881 Preliminary Data Book CONFIDENTIAL Revision 1.0 912-2000-031 December 13, 1999 ...
Page 2
Copyright Copyright © 1999 OPTi Inc. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, ...
Page 3
... Serial EEPROM MAP .........................................................................................................................................18 5.0 REGISTER DESCRIPTIONS .........................................................................................................................................19 5.1 OHCI AND US ANAGEMENT 5.2 FIFO C R ONFIGURATION EGISTERS 5.2.1 Tx FIFO-Related Registers.................................................................................................................................20 5.2.2 Rx FIFO-Related Registers ................................................................................................................................21 5.3 PCI C R ONFIGURATION EGISTERS 912-2000-031 Revision: 1 ABLE OF ONTENTS C ..................................................................................................................3 ONVENTIONS L .........................................................................................................................5 IST .................................................................................................................................. ....................................................................................19 ONTROL AND TATUS EGISTERS .................................................................................................................................19 ...................................................................................................................................23 FireLink 1394 OHCI 82C881 Page i ...
Page 4
... PCI Configuration Space (PCICFG 00h to 3Fh) ................................................................................................ 23 5 OWER ANAGEMENT EGISTERS 5 .................................................................................................................................................... 28 IMING NFORMATION 6.0 ELECTRICAL RATINGS............................................................................................................................................... 29 7.0 MECHANICAL PACKAGE............................................................................................................................................ 31 8.0 TEST MODES ............................................................................................................................................................... 33 9.0 APPENDIX A................................................................................................................................................................. 35 9 ........................................................................................................................................ 35 CRONYMS AND EFINITIONS 9.2 R ............................................................................................................................................................... 35 EFERENCES 10.0 APPENDIX B................................................................................................................................................................. 37 10.1 FIFO P ................................................................................................................................................... 37 ROGRAMMING 10.1.1 Programming Notes........................................................................................................................................... 37 10.1.2 Important User Defined Values.......................................................................................................................... 37 10.1.3 Current Default Configuration Values ................................................................................................................ 37 10 ...
Page 5
... Features The OPTi 82C881 1394 OHCI Link Controller is a PCI- based host controller with the following features. Compliant with PCI Local Bus Specification 2.1 Compliant with P1394a Draft 2.0 Standard for a High- performance Serial Bus Interfaces to 33MHz, 32-bit PCI bus PnP (Plug and Play) compatible per PCI Local Bus Specification rev ...
Page 6
... Page 2 912-2000-031 Revision: 1.0 ...
Page 7
... Analog Analog-level compatible CMOS CMOS-level compatible Dcdr Decoder Ext External G Ground I Input Int Internal I/O Input/Output Mux Multiplexer NIC No Internal Connection O Output OD Open drain P Power PD Pull-down resistor PU Pull-up resistor S Schmitt-trigger S/T/S Sustain Tristate TTL TTL-level compatible 912-2000-031 Revision: 1.0 FireLink 1394 OHCI 82C881 Page 3 ...
Page 8
... LQFP Pin Diagram (Note) Note: Figure 3-1 shows a pin diagram of the 82C881 packaged in an LQFP (Low-profile Quad Flat Pack, square). The device is also available in a QFP (Quad Flat Pack, rectangular). The pin assignment remains the same. Refer to Section 5, "Mechanical Package" for details regarding packaging. ...
Page 9
... GND 51 SERR# 52 PAR 53 C/BE1# 54 AD15 55 Vcc 56 AD14 57 AD13 58 AD12 59 AD11 60 GND 61 AD10 62 AD9 63 NIC 64 AD8 65 C/BE0# 66 AD7 67 AD6 68 AD5 82C881 Pin Signal Name Power No. Plane 69 AD4 VccCORE 70 Vcc 71 AD3 72 AD2 73 AD1 74 AD0 75 GND 76 RST# 77 TEST# 78 TMS# 79 ISOLATED# 80 Vcc 81 PHYDATA7 82 PHYDATA6 83 GND ...
Page 10
... Strapping Options 3.3.1 Test Mode Selection (Pins 77, 78) Pin 78, TMS# Pulled up Pulled down Pulled down 3.3.2 Serial EEPROM Presence Detect (Pin 5) Pin 5, SDA Pulled down Pulled up ® Page 6 Pin 77, TEST# Don't care Pulled down Pulled up Serial EEPROM Not present Present Function Normal Operation ...
Page 11
... FRAME# in the final data phase. FRAME input when the 82C881 is the target and an output when it is the initiator. FRAME# is tristated from the leading edge of RESET# and remains tristated until driven as either a master or slave by the 82C881 ...
Page 12
... TRDY# is tristated from the leading edge of RESET# and remains so until driven as either a master or a slave by the 82C881. Stop: STOP output when the 82C881 is the target and an input when it is the initiator. As the target, the 82C881 asserts STOP# to request that the master stop the current cycle ...
Page 13
... I/O sustained tristate signal and follows the PCI 2.1 defined protocol. Signal Description Link Request: This signal is used by the 82C881 to request access to the serial bus and to read or write PHY registers. Link-PHY Control Bus: These two signals are used by both the Link and PHY devices to transfer control information to and from each other ...
Page 14
... Page 10 Signal Description Test Mode Select: The 82C881 logic can be strapped into Test Mode for two types of tests: NAND tree and Boundary Scan. Details are provided in the Test Modes section of this document. This pin must be strapped high for Normal Operation. ...
Page 15
... OHCI and FIFO Configuration registers. Any packet coming from the 1394 serial bus is processed by the PHY, which then moves the data to the 82C881 per the 1394 packet format specification. According to the speed code received, data from data lines is read and converted to 32 bit quadlets ...
Page 16
... Block Diagram ® Page 12 912-2000-031 Revision: 1.0 ...
Page 17
... Serial EEPROM. Information like GUID, Device ID, Vendor ID, Class Code, Revision ID, Subsystem ID, and Subsystem Vendor ID can be stored in the Serial PROM. These are then loaded from the Serial EEPROM to the corresponding PCICFG registers at each power-on reset. 912-2000-031 Revision: 1.0 82C881 ® Page 13 ...
Page 18
... Arbiter Since there are seven DMA controllers, the 82C881 prioritizes the DMA controllers. To enable this functionality, the bus request signals from all the DMA contexts are fed into the arbiter, which in turn, based on the priorities specified in 1394 OHCI specification, decides on which DMA controller should get the grant. ...
Page 19
... Receive Block The Receive block deals with the packets in 1394 format, coming from the PHY to the 82C881. It takes data from the serial data lines, converts it into parallel 32-bit data, performs required checks on the data, converts the data to OHCI format and puts it into the appropriate FIFO. ...
Page 20
... Serial PROM. These values will be loaded from the Serial EEPROM after a power on reset if the 82C881 detects its presence through a pull up on the SDA pin. If the EEPROM is not present (SDA sensed LOW after reset), default values are loaded instead. ...
Page 21
... Starting address for transfer to or from EEPROM Reserved Reserved EEPROM Control Register EEPROM Data Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 82C881 2 1 Default = 00h Default = 00h Default = 00h Default = 00h ERROR Writing 1 Writing 1 initiates Write. initiates Read. 0: operation successful ...
Page 22
... Serial EEPROM MAP Byte Address Bit RSVD 1=Enable ® Page 18 Bit 6 Bit 5 Bit 4 MIN GNT[7:0] MAX LAT[7:0] SUBYSTEM VENDOR ID [7:0] SUBSYSTEM VENDOR ID [15:8] SUBYSTEM ID [7:0] SUBSYSTEM ID [15:8] Program ClkRun Interface Phy Reset 1=Enable Detection 1=Enable 1394 GUID HI [7:0] ...
Page 23
... Register Descriptions The 82C881 register set implements the OHCI registers, the FIFO Configuration registers, and the PCI bus configuration registers. 5.1 OHCI and Bus Management Control and Status Registers The OHCI Registers are memory mapped to Memory Base Address Register 1 (10h) and I/O mapped to I/O Base Address Register 1 (18h) of PCI Configuration space ...
Page 24
... Tx FIFO-Related Registers 7 6 OFST 00h Holds configuration data for Isochronous Transmit sub-FIFO Write Watermark bits [7: the number of empty quadlet space is equal to or greater than this value, the corresponding DMA controller can start a burst write into the FIFO. OFST 01h Read Watermark bits [5: the number of quadlets in the sub FIFO is greater than or equal to this value, the Link can start reading from that FIFO ...
Page 25
... Byte 0 Reserved Byte 1 Byte 2 Byte 3 Sub-FIFO Size bits [9:4] Physical Rx Request Configuration Register Byte 0 Reserved Byte 1 Byte 2 Byte 3 Sub-FIFO Size bits [9:4] 82C881 Default = 00h Default = 00h Reserved Default = 01h Read Watermark bits [9:6] Default = 20h Default = 00h Default = 00h Reserved Default = 01h ...
Page 26
... Note 1: All bits in this register default Hard Reset and Soft Reset; they are not affected by bus reset. Note 2: Software must set this bit load register changes to the FIFO Configuration registers. The 82C881 will clear this bit after the operation is complete. ...
Page 27
... PCI Configuration Registers The PCI Configuration space registers implemented in the 82C881 are listed in the following table. They are not affected by bus reset/soft reset. The configuration space of the PCI 1394 OHCI controller is accessed through Mechanism #1 as Device #X (Device # depends on which AD line is connected to the IDSEL input), Function #0, hereafter referred to as PCICFG. ...
Page 28
... PCICFG 07h Detected SERR# Received parity error: status: master abort status: This bit is set to This bit is set to 1 whenever the 1 whenever the Set to 1 when core detects a core detects a the core, acting parity error, PCI address as a PCI even if PCICFG parity error ...
Page 29
... Reserved CAP_ID Register (RO) Next_Item_Ptr Register (RO) PMC Register (RO) - Byte 0 Reserved PME Clock PME# clock required to generate PME# 82C881 2 1 Default = 00h Default = 0000h Default = 0000h Default = 00h Default = 44h Default = 00h Default = FFh Default = 01h Default = 01h Default = 05h Default = 00h ...
Page 30
... PCICFG 47h PME Support: 01000 = The Link controller supports PME# generation from D3 PCICFG 48h PCICFG 49h PCICFG 4Ah PCICFG 4Bh PME Status Data_Scale (RO): (R/W Data register is not This bit is set supported when a PME event is generated. Write 1 to clear. PCICFG 4Ch ...
Page 31
... Starting address for transfer to or from EEPROM Reserved Reserved EEPROM Control Register EEPROM Data Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 82C881 2 1 Default = 00h Default = 00h Default = 00h Default = 00h ERROR Writing 1 Writing 1 initiates Write. initiates Read. 0: operation successful ...
Page 32
... Timing Information The timing relations on the 82C881-PCI bus interface are per PCI Local Bus Specification Revision 2.1. The timing relations on the 82C881-PHY interface confirm to timings of Link-PHY interface of chapter 5, P1394a Draft 2.0 specification. ® Page 28 912-2000-031 Revision: 1.0 ...
Page 33
... Electrical Ratings 912-2000-031 Revision: 1.0 FireLink 1394 OHCI 82C881 Page 29 ...
Page 34
... Page 30 912-2000-031 Revision: 1.0 ...
Page 35
... Mechanical Package 912-2000-031 Revision: 1.0 FireLink 1394 OHCI 82C881 Page 31 ...
Page 36
... Page 32 912-2000-031 Revision: 1.0 ...
Page 37
... O Scan test output for PCI Trunk2 95 I Scan Test CLK for PHY Trunk 98 I Scan Test input for PHY trunk 97 O Scan Test Output for PHY Trunk FireLink 1394 OHCI 82C881 Signal Description Test Mode Select Test Scan Enable Page 33 ...
Page 38
... Page 34 912-2000-031 Revision: 1.0 ...
Page 39
... IEEE Std 1394-1995, Standard for High Performance Serial Bus. P1394a draft 2.0 Standard for a High performance Serial Bus. PCI Local Bus Specification Revision 2.1 IEEE Std 1212, 1994 edition. PCI Mobile Design Guide 1.1. PCI Power Management Specification 1.0. 912-2000-031 Revision: 1.0 FireLink 1394 OHCI 82C881 Page 35 ...
Page 40
... Page 36 912-2000-031 Revision: 1.0 ...
Page 41
... The size of each RAM module is 256 quadlets. Hence the address bus width is eight. It should be changed if the DPRAM size changes. For Rx FIFO RXFIFO_ADDRBUS_WIDTH. For Tx FIFO TXFIFO_ADDRBUS_WIDTH 10.1.3 Current Default Configuration Values Current Default Configuration Values and the reason for choosing them: 912-2000-031 Revision: 1 FireLink 1394 OHCI 82C881 Page 37 ...
Page 42
... Each DPRAM is of 256 quadlets, as obtained from the Vendor FIFO, each sub-FIFO Size is 64 quadlets FIFO, Combined FIFO is of 128 quadlets. This is because it contains packets for multiple packet types. Other two sub-FIFO’s have 64 quadlets each FIFO, WriteWatermark Value is chosen as 16 quadlets as PCI can support burst maximum of 16 quadlets. ...
Page 43
... Mbps, 010 – 400 Mbps This bit if set implies that the packet associated with this delimiter is a bus reset packet Thid bit is set if the packet associated with this start delimiter is a posted write packet. 82C881 ® Page 39 ...
Page 44
... Field Name Width Reserved 5 31:28 Receive packet end delimiter packet Field Name Width endDelimiter 1 0 error 1 1 selfIdIncomplete 1 2 Reserved 3 5:3 ackCode 4 9:6 FIFOFull 1 10 Reserved 22 31:10 The following is the format in which the Tx FIFO receives data (32 bit) from TxDMA. 10.2.1.2.4 Isochronous Receive Packet Format ® ...
Page 45
... Cycle count field of the Isochronous cycle timer register (refer to OHCI specification 1.0 chapter 5,section 5-12) Lower 3 bits of the Cycle seconds field of the Isochronous cycle timer register (refer to OHCI specification 1.0 chapter 5,section 5-12) CycleMatchEnable bit of the IT context control register Currently not used 82C881 ® Page 41 ...
Page 46
... Implementation For Debugging, the chip has debug mode. For this, bit 5 in miscReg of ohciRegVebdor.v is defined. It has to be asserted in order for the chip debug mode. Base Address Register 5 is assigned to be used for mapping the FIFOs. The identification of this base address Register done during PCI configuration cycle ...