sc9822p Silan, sc9822p Datasheet - Page 19

• Manufacturer Part Number: sc9822p
• Description: Mp3 Decoder With Esp Function And Cd Interface
• Manufacturer: Silan

(Continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
BitPoolPageLimitLow
[7:0]
ShockMsk[7:0]
Register in the Mmu module
MmuHostCmd[7:0]
Symbol
Address
0x5B
0x59
0x00
R/W
RW
W
W
Initialization
0x00
0x08
0xff
Shock signal shield register. Its unit is
128*59ns=7.552us, if the signal length is less
than input time, it is not consider the shock.
The max. shock shield time is 255x7.552us =
1,925.880 us.
Bit[2:0]: Control the Sdram operation.
Bit[3] : Enable Sdram initialization
Bit[7:4]
When use sdram, Bit[7:4] select Sdram type
4 >enable Sdram controllable refresh
7— > DRAM NORMAL MODE, before read or
0 >no operation
1 >control Sdram carry out Precharge
2 >control Sdram carry out CBR
3 > control Sdram set modes
5 >disable Sdram controllable refresh, but
6— >DRAM SELF-REFRESH MODE, only
0 > enable Sdram initialization, and do it in
1 > disable Sdram initialization,
*— > for DRAM, this bit is not care
0001 2BANK*(2048*256 => 512K)
0000 1BANK*(4096*256 => 1M*16)
enable Sdram auto refresh. When
Sdram not used in a period, but there
should remain the data, it can adopt this
mode,
dissipation.
for “ s” version dram. When enter this
mode for more than 100us, DRAM will
be in SELF-REFRESH state. you can
change mode only by set MmuHostCmd
BIT[2:0] to 7(that’ s change to normal
mode of dram)
write operation of DRAM, you should
enter NORMAL MODE for 200us for
DRAM initialization (auto execute
internal 8 cycles of refresh to initiate
dram device)
the control of Bit[2:0]
then
Description
reduce
REV:1.0
(To be continued)
SC9822P
Page 19 of 30
the
2006.07.21
power