Frequency Range
Frequency Stability
Operating Temperature
Storage Temperature
Supply Voltage
Supply Current
Output Symmetry
Rise and Fall Times (20/80%)
LVPECL Output Option
(DC coupling, 50 Ω to V
Low Power LVPECL Output Option
(AC coupling, 100 Ω Differential Load)
LVDS Output Option (2.5/3.3 V)
(R
LVDS Output Option (1.8 V)
(R
HCSL Output Option
CMOS Output Voltage
SSTL Output Voltage
Powerup Time
OE Deassertion to Clk Stop
Return from Output Driver Stopped Mode
Return From Tri-State Time
Return From Powerdown Time
Period Jitter (1-sigma)
Integrated Phase Jitter
Notes:
TERM
TERM
D
Features
Specifications
Rev. 0.2 9/08
1. Inclusive of 25 C° initial frequency accuracy, operating temperature range, supply voltage change, output load change, 1st year aging at
2. See AN409 for further details regarding output clock termination recommendations. SSTL minimum output voltage is minimum V
= 100 Ω diff)
= 100 Ω diff)
Quartz-free silicon oscillator
Any-rate output frequencies from 0.9 to 200 MHz
Quick turn delivery
Highly reliable startup and operation
Tri-state or power down operation
1.8, 2.5, or 3.3 V options
IFFERENTIAL
25 C°, shock and vibration.
maximum output voltage is maximum V
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Parameters
2
2
2
2
2
DD
– 2.0 V)
2
2
2
O
UTPUT
1.0 MHz – min(20 MHz, 0.4 x F
Differential CMOS(3.3 V option,10 pF,200 MHz)
1.0 MHz – min(20 MHz, 0.4 x F
OL
Copyright © 2008 by Silicon Laboratories
.
From time V
Differential CMOS, 15 pF, >80 MHz
HCSL/Differential SSTL
DC termination per pad
Low Power LVPECL
Differential SSTL-18
V
Differential SSTL-3
Differential SSTL-2
CMOS, C
V
OH
DD
LVPECL/LVDS
OL
Condition
S
See Note 1.
1.8 V option
2.5 V option
3.3 V option
Powerdown
Non-CMOS
, sourcing 9 mA
Diff swing
Diff swing
Diff swing
Diff swing
Diff swing
, sinking 9 mA
V
crosses min spec supply
Mid-level
Mid-level
Mid-level
Mid-level
Mid-level
SSTL-18
LVPECL
Tri-State
SSTL-2
SSTL-3
DIFF
HCSL
LVDS
I L I C O N
L
= 0
= 7 pF
LVPECL, LVDS, HCSL, differential CMOS,
and differential SSTL versions available
3.2 x 4.0 mm footprint compatible with
industry-standard 3.2 x 5.0 mm pinout
Low power
Pb-free and RoHS compliant
OUT
OUT
),CMOS format
),non-CMOS
O
SCILLATOR
.5 x V
.45 x V
46 – 13 ns/T
.5 x V
V
V
DD
DD
DD
Min
1.71
2.25
2.97
.720
1.15
0.25
0.85
0.25
0.35
0.65
DD
–55
0.9
.68
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
45
—
DD
—
—
—
—
—
—
—
—
—
0
– 1.5
– 0.6
+ 0.375
+ 0.48
+ 0.48
CLK
Typ
34.0
19.3
14.9
25.3
29.0
24.5
24.3
22.2
N/A
9.7
1.0
1.1
0.6
0.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Si500D
1
1
.5 x V
54 + 13 ns/T
.5 x V
.45 V
250 + 3 x T
250 + 3 x T
12 + 3 x T
V
DD
Max
±150
+125
DD
1.98
2.75
3.63
36.0
22.2
16.5
29.3
31.8
27.7
26.7
10.7
.880
1.26
0.45
0.96
0.45
.425
DD
200
+70
460
800
DD
1.9
1.6
.95
.82
0.6
1.5
25
55
—
—
– 1.34
2
2
2
3
1
– 0.375
– 0.48
– 0.48
CLK
CLK
CLK
CLK
OH
Si500D
. SSTL
ps RMS
ps RMS
ps RMS
ps RMS
Units
MHz
ppm
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
ms
C°
C°
ps
ps
ns
ns
ns
µs
%
V
V
V
V
V
V
V
V
Ω
V
V
V
V
V
PK
PK
PK
PK
PK