mx1ds10p- Centellax, mx1ds10p- Datasheet - Page 3

• Manufacturer Part Number: mx1ds10p-
• Description: 15 Ghz Ultra - Variable Broadband Prescaler
• Manufacturer: Centellax

Functional Block Diagram
SEED = A1 + (A2 x 2
Divide Ratio = 2
Freq
Pin Description
Port Name
CK
CKN
MSB
MSBN
A1,A2...A20
VCC
VEE
Paddle
out
= Freq
CENTELLAX
clk
20
/ (Divide Ratio)
Specifications subject to change without notice. Copyright © 2001-2008 Centellax, Inc. Printed in USA. 29 Feb 2008.
/ SEED (Lowest valid divide ratio = 2)
1
Description
Clock Input, Positive Terminal
Clock Input, Negative Terminal
Divided Output, Positive Terminal
Divided Output, Negative Terminal
Divide Ratio Selectors
RF & DC Ground
-3.3V @ 430mA
Backside of die
) + (A3 x 2
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2
) + .......+ (A20 x 2
19
) (Maximum valid SEED = 2
Negative CML signal levels
Negative CML signal levels
Negative CML signal levels
Negative CML signal levels
Divide ratio = Value of the binary seed A1...A20
Must be connected to good heatsink (see text)
Additional Comments
-
Negative Supply Voltage
19
)
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