upd16835 Renesas Electronics Corporation., upd16835 Datasheet - Page 18

• Manufacturer Part Number: upd16835
• Description: Monolithic Quad H Bridge Driver Circuit
• Manufacturer: Renesas Electronics Corporation.

CURRENT SET
<6th and 7th bytes>
initial mode, is to be used (CURRENT SET ).
(most significant bit) of the 7th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 s in units
of 0.25 s (with a 4-MHz clock).
when it is “1”, reference voltage 2 (EVR
of the initial data.
<8th byte>
output pin (EXT pin) is held at “L”.
18
Data
The 6th and 7th bytes select the pulse cycle of the
The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 6th byte, and bits D0 to D6
CURRENT SET is specified by bit D7 of the 7th byte. When this bit is “0”, reference voltage 1 (EVR
The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H.
If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the checksum
Table 5-12. 7th Byte Data Configuration (Standard data)
Bit
0 or 1
D7
Remark Bits D4 to D7 : Reference voltage 2 (EVR
Rotation direction
Most significant bit
0 or 1
D6
Data
Data
Bit
Bit
0 or 1
D5
Bits D0 to D3 : Reference voltage 1 (EVR
0 or 1
0 or 1
D7
D7
Table 5-11. 5th Byte Data Configuration (Standard data)
0 or 1
(Reference) 7th Byte Data Configuration for Initial Data
D4
0 or 1
0 or 1
0 or 1
ENABLE
D3
D6
D6
2
) is selected. For further information, refer to the description of the 7th byte
0 or 1
D2
Data Sheet G11594EJ2V0DS00
0 or 1
0 or 1
D5
D5
0 or 1
D1
channel and which of the two reference voltages, created in the
0 or 1
0 or 1
D4
D4
0 or 1
D0
Number of pulses
Table 5-13. 6th Byte Data Configuration (Standard data)
0 or 1
0 or 1
1
2
D3
D3
)
)
0 or 1
D7
0 or 1
0 or 1
0 or 1
D6
D2
D2
0 or 1
D5
0 or 1
0 or 1
D1
D1
0 or 1
D4
0 or 1
0 or 1
0 or 1
D0
D0
D3
Least significant bit
1
0 or 1
) is selected;
D2
PD16835
0 or 1
D1
0 or 1
D0