ds1075 ETC-unknow, ds1075 Datasheet - Page 11

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ds1075

Manufacturer Part Number
ds1075
Description
Econoscillator/divider
Manufacturer
ETC-unknow
Datasheet

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new transaction sequence can be started by re–initializ-
ing the device. Therefore to program both the DIV and
MUX registers two complete transaction sequences are
required.
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated
below. All time slots are initiated by the master driving
WRITE “1” TIME SLOT Figure 14
WRITE “0” TIME SLOT Figure 15
V
V
PULLUP MIN
PULLUP MIN
V
V
V
PULLUP
V
V
PULLUP
V
IL MAX
IH MIN
IL MAX
IH MIN
0V
0V
t
LOW1
15 s
15 s
60 s < t
1 s < t
1 s < t
60 s < t
1 s < t
LOW1
REC
SLOT
60 s
60 s
<
< 15 s
REC
< 120 s
SAMPLING WINDOW
SAMPLING WINDOW
LOW0
t
SLOT
t
LOW0
<
< t
DS1075
DS1075
SLOT
the data line low. The falling edge of the data line syn-
chronizes the DS1075 to the master by triggering a
delay circuit in the DS1075. During write time slots, the
delay circuit determines when the DS1075 will sample
the data line. For a read data time slot, if a “0” is to be
transmitted, the delay circuit determines how long the
DS1075 will hold the data line low overriding the 1 gen-
erated by the master. If the data bit is a “1”, the DS1075
will leave the read data time slot unchanged.
t
SLOT
< 120 s
t
REC
RESISTOR
MASTER
DS1075
t
REC
101697 11/16
DS1075

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