ds1848b-c50-t-r Maxim Integrated Products, Inc., ds1848b-c50-t-r Datasheet - Page 16

• Manufacturer Part Number: ds1848b-c50-t-r
• Description: Ds1848 Dual Temperature-controlled Nv Variable Resistor & Memory
• Manufacturer: Maxim Integrated Products, Inc.

NOTES
1) All voltages are referenced to ground.
2) Inputs SDA = SCL = WP = Vcc. A0, A1, and A2 must be tied to V
3) Valid at 25
4) Absolute linearity is the difference of measured value from expected value at DAC position.
5) Relative linearity the deviation of an LSB DAC setting change vs. the expected LSB change.
6) A fast mode device can be used in a standard mode system, but the requirement t
7) After this period, the first clock pulse is generated.
8) The maximum t
9) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
10) C
11) EEPROM write begins after a stop condition occurs.
12) The temperature coefficient varies with resistor position from 650ppm/°C at position FFh to
13) I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
14) Refer to Programming the Look-Up Table section of the data sheet for calibration.
15) Address input A1 passes Latch-up per JEDEC 78 class I. All other pins pass class II.
ORDERING INFORMATION
Expected value is a straight line from measured minimum position to measured maximum position.
Expected LSB change is the slope of the straight line from measured minimum position to measured
maximum position.
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next
data bit to the SDA line t
SCL signal.
VI
1000ppm/°C at 00h (for the 50k resistor), or 1500ppm/°C at 00h (for the 10k resistor). See the graphs
below. The tempco can be significantly reduced by using the resistor calibration values. When doing
so, the average tempco over the entire temperature range is between 200ppm/°C (for the lower
positions) and 10ppm/°C (higher positions). Refer to the Programming the Look-Up Table section of
the data sheet.
B
ORDERING
H MIN
— total capacitance of one bus line in picofarads, timing referenced to 0.9V
1500
1400
1300
1200
1100
1000
:
900
800
700
600
500
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
0
°
C only.
2000
TEMPCO vs. RESISTANCE
HD:DAT
RESISTANCE (OHMS)
10K RESISTOR
4000
has only to be met if the device does not stretch the LOW period (t
6000
RMAX
8000
+ t
PACKAGE
SU:DAT
10000
= 1000ns + 250ns = 1250ns before the SCL line is released.
16 of 17
1100
1000
900
800
700
600
500
0
10000
TEMPCO vs. RESISTANCE
OPERATING
RESISTANCE (OHMS)
50K RESISTOR
20000
CC
30000
or GND.
40000
CC
is switched off.
CC
50000
and 0.1V
SU:DAT
VERSION
> 250ns must
LOW
CC
.
) of the