ds1553p-85 Maxim Integrated Products, Inc., ds1553p-85 Datasheet - Page 4

• Manufacturer Part Number: ds1553p-85
• Description: 64kb, Nonvolatile, Year-2000-compliant Timekeeping Ram
• Manufacturer: Maxim Integrated Products, Inc.

Table 1. Operating Modes
DATA READ MODE
The DS1553 is in read mode whenever
device architecture allows ripple-through access to any valid address location. Valid data is available at
the data input/output (DQ) pins within t
access times are satisfied. If
chip-enable access (t
t
output data hold time (t
DATA WRITE MODE
The DS1553 is in write mode whenever
referenced to the latter occurring transition of
the cycle.
read or write cycle. Data in must be valid t
afterward. In a typical application, the
provided that care is taken with the data bus to avoid bus contention. If
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on
DATA RETENTION MODE
The 5V device is fully accessible, and data can be written and read only when V
However, when V
internal clock registers and SRAM are blocked from any access. When V
point V
battery. RTC operation and SRAM data are maintained from the battery until V
levels.
The 3.3V device is fully accessible and data can be written and read only when V
When V
switched from V
than V
CE
AA
. If the address inputs are changed while
V
and
SO
V
SO
CC
< V
SO
<V
V
CC
OE
, the device power is switched from V
> V
CC
BAT
CC
(battery supply level), device power is switched from the V
CE
falls below V
. If the outputs are activated before t
PF
<V
WE
PF
and
CC
will then disable the outputs t
CC
WE
to the internal backup lithium battery when V
CEA
is below the power-fail point (V
CE
V
V
V
V
X
X
OH
IH
IL
IL
IL
must return inactive for a minimum of t
) or at output-enable access time (t
PF
) but will then go indeterminate until the next address access.
, access to the device is inhibited. If V
OE
V
V
X
X
X
X
CE
IH
IL
or
WE
V
V
V
X
X
X
OE
IH
IH
IL
OE
AA
access times are not met, valid data is available at the latter of
CE
signal is high during a write cycle. However,
after the last address input is stable, provided that
WE
DQ0–DQ7
DS
(chip enable) is low and
High-Z
High-Z
High-Z
High-Z
WEZ
CE
WE
CC
D
and
D
AA
prior to the end of the write and remain valid for t
OUT
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IN
to the internal backup lithium battery when V
, the data lines are driven to an intermediate state until
after
and
or
CE
PF
)—the point at which write protection occurs—the
CE
OE
are in their active state. The start of a write is
WE
. The addresses must be held valid throughout
OEA
remain valid, output data remains valid for
Data Retention
goes active.
). The state of the DQ pins is controlled by
Deselect
Deselect
WR
MODE
Write
Read
Read
PF
CC
prior to the initiation of a subsequent
is less than V
CC
drops below V
pin to the internal backup lithium
WE
CC
falls below the battery switch
(write enable) is high. The
CMOS Standby
Battery Current
OE
CC
POWER
Standby
SO
Active
Active
Active
CC
CC
is returned to nominal
is low prior to
, the device power is
PF
is greater than V
is greater than V
. If V
OE
can be active
PF
CE
is greater
CC
and
drops
WE
OE
PF
PF
DH
.
.