ds21372 Maxim Integrated Products, Inc., ds21372 Datasheet - Page 11

• Manufacturer Part Number: ds21372
• Description: Ds21372 3.3v Bit Error Rate Tester Bert
• Manufacturer: Maxim Integrated Products, Inc.

REPETITIVE PATTERN GENERATION (PCR.5=0) Table 5
Notes For Tables 4 and 5:
1. PTR = Polynomial Tap Register (address = 05)
2. PLR = Pattern Length Register (address = 04)
3. PSR3 = Pattern Set Register 3 (address = 00)
4. PSR2 = Pattern Set Register 2 (address = 01)
5. PSR1 = Pattern Set Register 1 (address = 02)
6. PSR0 = Pattern Set Register 0 (address = 03)
7. TINV = Transmit Data Inversion Select Bit (EIR.5)
8. RINV = Receive Data Inversion Select Bit (EIR.4)
9. For the 2
8. BIT COUNT REGISTERS
The Bit Count Registers (BCR3 to BCR0) comprise a 32-bit count of bits (actually RCLK cycles)
received at RDATA. BC31 is the MSB of the 32-bit count. The bit counter increments for each cycle of
RCLK when input pin RDIS is low. The bit counter is disabled during loss of SYNC. The Status Register
bit BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the
BCR by either toggling the LC bit or pin. The DS21372 latches the bit count into the BCR registers and
clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The
bit count and bit error count (available via the BECRs) are used by an external processor to compute the
BER performance on a loop or channel basis.
PATTERN TYPE
all 1s
all 0s
alternating 1s and 0s
double alternating 1s and 0s
3 in 24
1 in 16
1 in 8
1 in 4
D4 Line Loopback Activate
D4 Line Loopback Deactivate
2
32
- 1.
32
-1 pattern, the random pattern actually repeats every (4093 x 2
PTR
00
00
00
00
00
00
00
00
00
00
PLR
00
00
01
03
17
0F
07
03
04
02
11 of 22
PSR3 PSR2 PSR1 PSR0 TINV RINV
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
20
FF
FF
FF
FF
FF
FF
FF
FF
00
00
20
) + 1046529 bits instead of
FE
FE
FC
FC
FF
F1
F0
22
01
01
0
0
0
0
0
0
0
0
0
0
DS21372
0
0
0
0
0
0
0
0
0
0