ds2760bx-025-t-r Maxim Integrated Products, Inc., ds2760bx-025-t-r Datasheet - Page 20

• Manufacturer Part Number: ds2760bx-025-t-r
• Description: Ds2760 High-precision Li+ Battery Monitor
• Manufacturer: Maxim Integrated Products, Inc.

I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2760 are: the initialization sequence (Reset Pulse followed by Presence Pulse), Write 0, Write 1, and
Read Data. All of these types of signaling except the Presence Pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2760 is shown in Figure 17.
A Presence Pulse following a Reset Pulse indicates the DS2760 is read to accept a Net Address
Command. The bus master transmits (Tx) a Reset Pulse for t
and goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pull-up resistor. After
detecting the rising edge on the DQ pin, the DS2760 waits for t
for t
1-WIRE INITIALIZATION SEQUENCE Figure 17
WRITE TIME SLOTS
A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic high (inactive) level to
a logic low level. There are two types of write time slots: Write 1 and Write 0. All write time slots must
be t
DS2760 samples the 1-Wire bus line between 15
sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 18). For the bus
master to generate a Write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15
slot, the bus line must be pulled low and held low for the duration of the write time slot.
READ TIME SLOTS
A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to a
logic low level. The bus master must keep the bus line low for at least 1
DS2760 to present valid data. The bus master can then sample the data t
read time slot. By the end of the read time slot, the DS2760 releases the bus line and allows it to be
pulled high by the external pull-up resistor. All read time slots must be t
with a 1
SLOT
PDL
DQ
.
m
(60
s minimum recovery time, t
m
s to 120
LINE TYPE LEGEND:
m
s) in duration with a 1
m
t
RSTL
Bus master active low
Both bus master and
DS2760 active low
s after the start of the write time slot. For the host to generate a Write 0 time
t
PDH
REC
, between cycles. See Figure 18 for more information.
m
s minimum recovery time, t
m
s and 60
20
t
PDL
m
s after the line falls. If the line is high when
RSTL
DS2760 active low
Resistor pullup
PDH
t
RSTH
. The bus master then releases the line
and then transmits the Presence Pulse
m
SLOT
s and then release it to allow the
RDV
(60
(15
REC
m
m
, between cycles. The
s to 120 m s) in duration
s) from the start of the
PACK+
PACK–