ds2782 Maxim Integrated Products, Inc., ds2782 Datasheet
ds2782
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ds2782 Summary of contents
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... GENERAL DESCRIPTION The DS2782 measures voltage, temperature and current, and estimates available rechargeable lithium ion and lithium-ion polymer batteries. Cell characteristics parameters used in the calculations are stored in on- chip EEPROM. The available capacity registers report a conservative estimate of the amount of ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to V Voltage on V Relative Operating Temperature Range Storage Temperature Range Soldering Temperature Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to ...
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PARAMETER Current Gain Error Current Offset Error Accumulated Current Offset Timebase Error ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (2.5V ≤ V ≤ 5.5V -20°C to +70°C PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START ...
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... Note 3: Factory calibrated accuracy. Higher accuracy can be achieved by in-system calibration by the user. Note 4: Accumulation bias register set to 00h. Note 5: Parameters guaranteed by design. Note 6: Timing must be fast enough to prevent the DS2782 from entering sleep mode due to bus low for period > SLEEP Note 7: f must meet the minimum clock low time plus the rise/fall times ...
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PIN DESCRIPTION TSSOP TDFN NAME PIN PIN VSS VIN 3 4 VDD 4 5 SDA 5 6 SCL 6 7 N.C. — 8 SNS 7 9 PIO 8 10 PAD — PAD Not Connected. ...
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... SNS DETAILED DESCRIPTION The DS2782 operates directly from 2.5V to 5.5V and supports single cell Lithium-ion battery packs. As shown in Figure 3, the DS2782 accommodates multicell applications by adding a voltage regulator for VDD and voltage divider for VIN. Nonvolatile storage is provided for cell compensation and application parameters. Host side development of fuel-gauging algorithms is eliminated ...
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... Note: PMOD and UVEN SLEEP features must be disabled when a battery is charged on an external charger that does not connect to SDA and/or SCL. PMOD SLEEP can be used if the charger pulls the bus high. The DS2782 remains in SLEEP and therefore does not measure or accumulate current when a battery is charged on a charger that fails to properly drive the communication bus ...
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... If the bus was low, it must be pulled up before a START bit can be issued by the master as required with PMOD SLEEP. If the bus was high when UVEN SLEEP was entered, then the DS2782 is prepared to receive a START bit from the master. A standard procedure of issuing a START – STOP – START when the host system is powered up on the charger input properly initiates communication from both PMOD and UVEN SLEEP modes ...
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... CURRENT MEASUREMENT In the ACTIVE mode of operation, the DS2782 continually measures the current flow into and out of the battery by measuring the voltage drop across a low-value current-sense resistor, R SNS and VSS is ±51.2mV. The input linearly converts peak signal amplitudes up to 102.4mV as long as the continuous signal level (average over the conversion cycle period) does not exceed ± ...
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... SENSE RESISTOR TEMPERATURE COMPENSATION The DS2782 is capable of temperature compensating the current sense resistor to correct for variation in a sense resistor’s value over temperature. The DS2782 is factory programmed with the sense resistor temperature coefficient, RSTC, set to zero, which turns off the temperature compensation function ...
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... The AB can be used to account for currents that do not flow through the sense resistor, estimate currents too small to measure, estimate battery self-discharge or correct for static offset of the individual DS2782 device. The AB register allows a user programmed constant positive or negative polarity bias to be included in the current accumulation process. The user-programmed two’ ...
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Figure 10. Accumulation Bias Register Formats CAPACITY ESTIMATION ALGORITHM Remaining capacity estimation uses real-time measured values and stored parameters describing the cell characteristics and application operating limits. The following diagram describes the algorithm inputs and outputs. Figure 11. Top Level ...
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... AN131 is used to store cell characteristics in the DS2782. Full and empty points are retrieved in a lookup process which re-traces a piece-wise linear model. Three model curves are stored: Full, Active Empty and Standby Empty. Each model curve is constructed with 4 line segments and spans from 0° ...
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... The standby load current and voltage are used for determining the cell characteristics but are not programmed into the DS2782. The DS2782 reconstructs the Standby Empty line from cell characteristic table values to determine the Standby Empty capacity of the battery at each temperature. ...
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... AS, however caution should exercised when writing AS to ensure that the cumulative aging estimate is not over written with an incorrect value. Usually, writing AS by the host is not necessary because AS is automatically saved to EEPROM on a periodic basis by the DS2782. (See the Memory section for details.) The EEPROM stored value recalled on power-up. ...
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... RESULT REGISTERS The DS2782 processes measurement and cell characteristics on a 3.5s interval and yields seven result registers. The result registers are sufficient for direct display to the user in most applications. The host system can produce customized values for system use, or user display by combining measurement, result and User EEPROM values. ...
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... UVF 1 Read / Write * PORF 0 Read Only Reserved * - This bit can be set by the DS2782, and may only be cleared via the 2-Wire interface LEARNF is only cleared if ACR reaches 0 after VOLT < VAE. {(AS * FULL(T) - AE(T)) * FULL40[mVh]} {(AS * FULL(T) - SE(T)) * FULL40[mVh]} Bit Definition Allowable Values Charge Termination Flag Set to 1 when: ( VOLT > VCHG ) AND ( 0 < IAVG < IMIN ) continuously for a period between two IAVG register updates ( 28s to 56s ). Cleared to 0 when: RARC < ...
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CONTROL REGISTER All CONTROL register bits are read and write accessible. The CONTROL register is recalled from Parameter EEPROM memory at power-up. Register bit values can be modified in shadow RAM after power-up. Shadow RAM values can be saved as ...
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... The new slave address value is effective following the write to 7Eh, and must be used to address the DS2782 on subsequent bus transactions. The slave address value is not stored to EEPROM until a Copy EEPROM block 1 command is executed. Prior to executing the Copy command, power cycling the DS2782 restores the original slave address value ...
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... The ACR (MSB and LSB) and AS registers are automatically saved to EEPROM when the RARC result crosses 4% boundaries. This allows the DS2782 to be located outside the protection FETs. In this manner protection device is triggered, the DS2782 cannot lose more that 4% of charge or discharge data. ...
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Table 2. MEMORY MAP ADDRESS (HEX) 00 Reserved 01 STATUS - Status Register 02 RAAC - Remaining Active Absolute Capacity MSB 03 RAAC - Remaining Active Absolute Capacity LSB 04 RSAC - Remaining Standby Absolute Capacity MSB 05 RSAC - ...
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... DS2782 slave device and a master device at speeds up to 400 kHz. The DS2782’s SDA pin operates bi-directionally, that is, when the DS2782 receives data, SDA operates as an input, and when the DS2782 returns data, SDA operates as an open drain output, with the host system providing a resistive pull-up. ...
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... R selects a read transaction, with the following bytes being read from the stave by the master. Bus Timing The DS2782 is compatible with any bus timing up to 400kHz. No special configuration is required to operate at any speed. 2-Wire Command Protocols The command protocols involve several transaction formats ...
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... Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2782 throughout the transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding to the last byte it requires with a No Acknowledge. This signals the DS2782 that control of SDA is to remain with the master following the Acknowledge clock. ...
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... The DS2782 can be special ordered with a unique, factory-programmed ID that is 64 bits in length. The first eight bits are the product family code (B2h for DS2782). The next 48 bits are a unique 40-bit serial number followed by 0x82h. The last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 16). The 64-bit ID can be read as 8 bytes starting at memory address F0h ...