ds2786 Maxim Integrated Products, Inc., ds2786 Datasheet - Page 19

• Manufacturer Part Number: ds2786
• Description: Ds2786 Standalone Ocv-based Fuel Gauge
• Manufacturer: Maxim Integrated Products, Inc.

DS2786 Standalone OCV-Based Fuel Gauge
Bus Idle
The bus is defined to be idle, or not busy, when no master device has control. Both SDA and SCL remain high
when the bus is idle. The STOP condition is the proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condition (S), by forcing a high-to-low transition on SDA while SCL
is high. The master terminates a transaction with a STOP condition (P), a low-to-high transition on SDA while SCL
is high. A Repeated START condition (Sr) can be used in place of a STOP then START sequence to terminate one
transaction and begin another without returning the bus to the idle state. In multimaster systems, a Repeated
START allows the master to retain control of the bus. The START and STOP conditions are the only bus activities
in which the SDA transitions when SCL is high.
Acknowledge Bits
Each byte of a data transfer is acknowledged with an Acknowledge bit (A) or a No Acknowledge bit (N). Both the
master and the DS2786 slave generate acknowledge bits. To generate an Acknowledge, the receiving device must
pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until SCL
returns low. To generate a No Acknowledge (also called NAK), the receiver releases SDA before the rising edge of
the acknowledge-related clock pulse and leaves SDA high until SCL returns low. Monitoring the acknowledge bits
allows for detection of unsuccessful data transfers. An unsuccessful data transfer can occur if a receiving device is
busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should re-
attempt communication.
Data Order
A byte of data consists of 8 bits ordered most significant bit (MSB) first. The least significant bit (LSB) of each byte
is followed by the Acknowledge bit. DS2786 registers composed of multibyte values are ordered most significant
byte (MSB) first. The MSB of multibyte registers is stored on even data memory addresses.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by a Slave
Address (SAddr) and the read/write (R/W) bit. When the bus is idle, the DS2786 continuously monitors for a
START condition followed by its slave address. When the DS2786 receives a slave address that matches its Slave
Address, it responds with an Acknowledge bit during the clock period following the R/W bit. The factory default 7-bit
2
Slave Address is 0110110. The upper 3 bits are fixed at 011, the lower 4 bits can be changed by writing the I
C
Address Configuration Register at location 7Dh.
2
Figure 24. I
C Address Configuration Register Format
ADDRESS 7Dh
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDR3
ADDR2
ADDR1
ADDR0
X
X
X
X
X—Reserved.
2
ADDR3:0—User-adjustable bits of the DS2786’s I
C address. Factory default is 0110.
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