ds2437 Maxim Integrated Products, Inc., ds2437 Datasheet - Page 24

• Manufacturer Part Number: ds2437
• Description: Smart Battery Monitor
• Manufacturer: Maxim Integrated Products, Inc.

DS2437
I/O SIGNALING
The DS2437 requires strict protocols to insure data integrity. The protocol consists of several types of
signaling on one line: reset pulse, presence pulse, write 0, write 1, read 0, and read 1. All of these signals,
with the exception of the presence pulse, are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2437 is shown in Figure 9.
A reset pulse followed by a presence pulse indicates the DS2437 is ready to send or receive data given the
correct ROM command and memory function command.
The bus master transmits (Tx) a reset pulse (a low signal for a minimum of 480 s). The bus master then
releases the line and goes into a receive mode (Rx). The 1-Wire bus is pulled to a high state via the
5 k =pullup resistor. After detecting the rising edge on the I/O pin, the DS2437 waits 15-60 s and then
transmits the presence pulse (a low signal for 60-240 s). DS2437 data is read and written through the
use of time slots to manipulate bits and a command word to specify the transaction.
INITIALIZATION PROCEDURE "RESET AND PRESENCE PULSES" Figure 9
Write Time Slots
A write time slot is initiated when the host pulls the data line from a high (inactive) logic level to a low
logic level. There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write
time slots must be a minimum of 60 s in duration with a minimum of a 1 s recovery time between
individual write cycles.
The DS2437 samples the I/O line in a window of 15 s to 60 s after the I/O line falls. If the line is high,
a Write 1 occurs. If the line is low, a Write 0 Occurs (See Figure 10).
For the host to generate a Write 1 time slot, the data line must be pulled to a logic low level and then
released, allowing the data line to pull up to a high level within 15 microseconds after the start of the
write time slot.
For the host to generate a Write 0 time slot, the data line must be pulled to a logic low level and remain
low for the duration of the write time slot.
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