ds2423 Maxim Integrated Products, Inc., ds2423 Datasheet
ds2423
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ds2423 Summary of contents
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... DESCRIPTION ® The DS2423 1-Wire RAM with Counters is a fully static, read/write memory for battery operation in a low-cost, six-lead TSOC, surface-mount package. The memory is organized as 16 pages of 256 bits each. In addition, the device has four counters, two of them with external trigger inputs called A and B. Each of the counters is associated with a memory page ...
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... LASERED ROM Each DS2423 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (See Figure 3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4 ...
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... BLOCK DIAGRAM Figure 1 ADDRESS REGISTERS AND TRANSFER STATUS Because of the serial data transfer, the DS2423 employs three address registers called TA1, TA2, and E/S (Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte counter and Transfer Status register ...
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... HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 DS2423 SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 7) 64-BIT LASERED ROM Figure 3 MSB 8-BIT CRC CODE MSB 1-WIRE CRC GENERATOR Figure 4 DS2423 48-BIT SERIAL NUMBER LSB MSB 8-BIT FAMILY CODE (1DH = DS2423) LSB MSB LSB ...
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... TA1, TA2 and E/S. The master may obtain the contents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. As soon as the DS2423 has received these bytes correctly, it will copy the data to the requested location beginning at the target address. ...
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Read Scratchpad Command [AAH] This command is used to verify scratchpad data and target address. After issuing the Read Scratchpad command, the master begins reading. The first 2 bytes will be the target address. The next byte will be the ...
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... DS2423 MEMORY MAP Figure 5 ADDRESS REGISTERS Figure ...
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... After the 16-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2423 until a Reset Pulse is issued. The Read Memory + Counter command sequence can be ended at any point by issuing a Reset Pulse ...
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... TX Reset? Master RX "1" transmitted or received at Overdrive speed Reset Pulse to be transmitted at Overdrive speed Reset Pulse to be transmitted at normal speed the DS2423 reset from Overdrive speed to regular speed. 1) From ROM Functions Flow Chart (Figure 9) ...
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... transmitted or received at Overdrive speed Reset Pulse to be transmitted at Overdrive speed Reset Pulse to be transmitted at normal speed the DS2423 reset from Overdrive speed to regular speed Figure 7 F0H rd 3 Part Read ...
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... Master TX Reset transmitted or received at Overdrive speed Reset Pulse to be transmitted at Overdrive speed Reset Pulse to be transmitted at normal speed the DS2423 reset from Overdrive speed to regular speed DS2423 Increments Address Counter Master TX Reset? ...
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MEMORY FUNCTION EXAMPLE Example: Write two data bytes to memory location 0026 and 0027. Read entire memory. MASTER MODE DATA (LSB FIRST <2 data bytes> ...
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MEMORY FUNCTION EXAMPLE Read page 14 and counts of Input A. Rewrite page 14 with 32 bytes. Read Memory + Counter, Write Scratchpad, Copy Scratchpad. MASTER MODE DATA (LSB FIRST <32 data bytes> ...
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... To facilitate this, each device attached to the 1-Wire bus must have open- drain or 3-state outputs. The 1-Wire port of the DS2423 is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At regular speed the 1-Wire bus has a maximum data rate of 16 ...
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... Reset Pulse transmitted by the bus master followed by Presence Pulse(s) transmitted by the slave(s). The Presence Pulse lets the bus master know that the DS2423 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the six ROM function commands ...
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... The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive speed, allows the bus master to address a specific DS2423 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS2423 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command ...
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... F0H N Match Search ROM? ROM? Y DS2423 TX Bit 0 1) DS2423 TX Bit 0 Master TX Bit Bit 0 Match? Bit 0 Match? Y DS2423 TX Bit 1 1) DS2423 TX Bit 1 Master TX Bit Bit 1 Match? Bit 1 Match? Y DS2423 TX Bit 63 1) DS2423 TX Bit 63 Master TX Bit Bit 63 Match? Bit 63 Match? ...
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ROM FUNCTIONS FLOW CHART Figure 9 cont’d To Figure Part From Figure Part From Figure Part 3) To Figure Part N CCH 3CH Skip Overdrive ROM? Skip ROM? ...
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... DS2423. During write time slots, the delay circuit determines when the DS2423 will sample the data line. For a read data time slot “0” transmitted, the delay circuit determines how long the DS2423 will hold the data line low overriding the 1 generated by the master. If the data bit is a “ ...
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... READ/WRITE TIMING DIAGRAM Figure 11 Write-One Time Slot T V LOW1 PUP V PUPMIN LOW1 0V RESISTOR Write-Zero Time Slot V PUP V PUPMIN V IHMIN V ILMAX 0V RESISTOR t SLOT MASTER t SLOT t L0W0 MASTER REC DS2423 t REC DS2423 ...
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... ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2423 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial ...
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CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated ...
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AC CHARACTERISTICS REGULAR SPEED PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low ...
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NOTES: 1) All voltages are referenced to ground external pullup voltage. PUP 3) Input load is to ground additional reset or communication sequence cannot begin until the reset high time has expired. 5) Read data ...