ds90cf365mtd National Semiconductor Corporation, ds90cf365mtd Datasheet

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ds90cf365mtd

Manufacturer Part Number
ds90cf365mtd
Description
+3.3v Programmable Lvds Transmitter 24-bit Flat Panel Display Fpd Link-85 Mhz, +3.3v Programmable Lvds Transmitter 18-bit Flat Panel Display Fpd L
Manufacturer
National Semiconductor Corporation
Datasheet
© 2003 National Semiconductor Corporation
DS90C385/DS90C365
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-85 MHz, +3.3V Programmable LVDS
Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz
General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/
LVTTL data into four LVDS (Low Voltage Differential Signal-
ing) data streams. A phase-locked transmit clock is transmit-
ted in parallel with the data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are
sampled and transmitted. At a transmit clock frequency of 85
MHz, 24 bits of RGB data and 3 bits of LCD timing and
control data (FPLINE, FPFRAME, DRDY) are transmitted at
a rate of 595 Mbps per LVDS data channel. Using a 85 MHz
clock, the data throughput is 297.5 Mbytes/sec. Also avail-
able is the DS90C365 that converts 21 bits of LVCMOS/
LVTTL data into three LVDS (Low Voltage Differential Sig-
naling) data streams. Both transmitters can be programmed
for Rising edge strobe or Falling edge strobe through a
dedicated pin. A Rising edge or Falling edge strobe transmit-
ter will interoperate with a Falling edge strobe Receiver
(DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch
ball grid array (FBGA) package which provides a 44 %
reduction in PCB footprint compared to the TSSOP package.
Block Diagrams
TRI-STATE
Order Number DS90C385MTD or DS90C385SLC
See NS Package Number MTD56 or SLC64A
®
is a registered trademark of National Semiconductor Corporation.
DS90C385
DS100868
10086801
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high-speed TTL interfaces.
Features
n 20 to 85 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption
n Tx Power-down mode
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 2.38 Gbps throughput
n Up to 297.5 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
n DS90C385 also available in a 64 ball, 0.8mm fine pitch
Grayscale
ball grid array (FBGA) package
See NS Package Number MTD48
Order Number DS90C365MTD
DS90C365
<
<
200µW (max)
130 mW (typ)
@
85MHz
www.national.com
10086829
May 2003

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ds90cf365mtd Summary of contents

Page 1

... Block Diagrams DS90C385 Order Number DS90C385MTD or DS90C385SLC See NS Package Number MTD56 or SLC64A TRI-STATE is a registered trademark of National Semiconductor Corporation. ® © 2003 National Semiconductor Corporation This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. ...

Page 2

Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration Junction Temperature ...

Page 3

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case DS90C365 ICCTG Transmitter Supply Current 16 Grayscale DS90C365 ICCTZ Transmitter Supply Current Power Down Note 1: “Absolute ...

Page 4

Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol TPPos0 Transmitter Output Pulse Position for Bit 0 (Figures 13, 14) (Note 5) TPPos1 Transmitter Output Pulse Position for Bit 1 TPPos2 Transmitter Output Pulse Position ...

Page 5

AC Timing Diagrams (Continued) FIGURE 2. “16 Grayscale” Test Pattern - DS90C385 (Notes 8, 9, 10) 5 10086805 www.national.com ...

Page 6

AC Timing Diagrams FIGURE 3. “16 Grayscale” Test Pattern - DS90C365 (Notes 8, 9, 10) Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 8: The 16 grayscale test ...

Page 7

AC Timing Diagrams (Continued) FIGURE 6. DS90C385/DS90C365 (Transmitter) Input Clock Transition Time FIGURE 7. DS90C385/DS90C365 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) FIGURE 8. DS90C385/DS90C365 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90C385/DS90C365 (Transmitter) Phase Lock Loop ...

Page 8

AC Timing Diagrams FIGURE 10. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90C385 FIGURE 11. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90C365 www.national.com (Continued) FIGURE 12. Transmitter Power Down Delay 8 10086817 10086832 ...

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AC Timing Diagrams (Continued) FIGURE 13. Transmitter LVDS Output Pulse Position Measurement - DS90C385 9 10086826 www.national.com ...

Page 10

AC Timing Diagrams FIGURE 14. Transmitter LVDS Output Pulse Position Measurement - DS90C365 www.national.com (Continued) FIGURE 15. TJCC Test Setup - DS90C385 Shown 10 10086833 10086827 ...

Page 11

AC Timing Diagrams FIGURE 16. Timing Diagram of the Input cycle-to-cycle clock jitter DS90C385 MTD56 (TSSOP) Package Pin Description — FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 ...

Page 12

DS90C385SLC SLC64A (FBGA) Package Pin Summary — FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. TxOUT Positive LVDS differential data output. TxOUT− Negative LVDS differential data output. TxCLKIN I 1 TTL ...

Page 13

DS90C385SLC SLC64A (FBGA) Package Pin Description — FPD Link Transmitter (Continued) By Pin D4 TxOUT1+ D5 LVDS GND D6 PLL GND D7 PWD DOWN D8 TxIN26 E1 VCC E2 TxIN6 E3 TxIN7 E4 GND E5 TxIN16 E6 VCC E7 TxIN24 ...

Page 14

DS90C365 Pin Description — FPD Link Transmitter Pin Name I/O No. TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, ...

Page 15

... A floating/terminated clock input will result in a LOW clock output. 10086823 Typical Application Condition Strobe Status R_FB = V Rising edge strobe CC R_FB = GND or NC Falling edge strobe 15 DS90CF365MTD 10086824 10086803 www.national.com ...

Page 16

Physical Dimensions 56-Lead Molded Thin Shrink Small Outline Package, JEDEC 48-Lead Molded Thin Shrink Small Outline Package, JEDEC www.national.com inches (millimeters) unless otherwise noted Dimensions in millimeters only Order Number DS90C385MTD NS Package Number MTD56 Dimensions in millimeters only Order ...

Page 17

... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...

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