74AC273MTCX Fairchild Semiconductor, 74AC273MTCX Datasheet

IC FLIP FLOP OCT D TYPE 20TSSOP

74AC273MTCX

Manufacturer Part Number
74AC273MTCX
Description
IC FLIP FLOP OCT D TYPE 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ACr
Type
D-Type Busr
Datasheet

Specifications of 74AC273MTCX

Function
Master Reset
Output Type
Non-Inverted
Number Of Elements
1
Number Of Bits Per Element
8
Frequency - Clock
175MHz
Delay Time - Propagation
5.5ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Logic Family
AC
Technology
CMOS
Number Of Bits
8
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Polarity
Non-Inverting
Operating Supply Voltage (typ)
2.5/3.3/5V
Package Type
TSSOP
Propagation Delay Time
14.5ns
Low Level Output Current
24mA
High Level Output Current
-24mA
Frequency (max)
125MHz
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Rev. 1.6.0
74AC273, 74ACT273
Octal D-Type Flip-Flop
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74AC273SC
74AC273SJ
74AC273MTC
74AC273PC
74ACT273SC
74ACT273SJ
74ACT273MTC
Order Number
Ideal buffer for microprocessor or memory
Eight edge-triggered D-type flip-flops
Buffered common clock
Buffered, asynchronous master reset
See 377 for clock enable version
See 373 for transparent latch version
See 374 for 3-STATE version
Outputs source/sink 24mA
74ACT273 has TTL-compatible inputs
All packages are lead free per JEDEC: J-STD-020B standard.
Package
Number
MTC20
MTC20
M20B
M20D
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
General Description
The AC273 and ACT273 have eight edge-triggered
D-type flip-flops with individual D-type inputs and Q
outputs. The common buffered Clock (CP) and Master
Reset (MR) input load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each
D-type input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-
flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output
only is required and the Clock and Master Reset are
common to all storage elements.
Package Description
January 2008
www.fairchildsemi.com

Related parts for 74AC273MTCX

74AC273MTCX Summary of contents

Page 1

... MTC20 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Rev. 1.6.0 General Description The AC273 and ACT273 have eight edge-triggered D-type flip-flops with individual D-type inputs and Q outputs ...

Page 2

... Data Outputs 0 7 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Rev. 1.6.0 Logic Symbols IEEE/IEC Mode Select-Function Table Inputs Operating Mode ...

Page 3

... V Output Voltage O T Operating Temperature Minimum Input Edge Rate, AC Devices: V from 30 Minimum Input Edge Rate, ACT Devices: V from 0.8V to 2.0V ©1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Rev. 1.6.0 Parameter Parameter , V @ 3.3V, 4.5V, 5. 4.5V, 5. Rating –0.5V to +7.0V –20mA +20mA –0. 0.5V CC – ...

Page 4

... Notes: 1. All outputs loaded; thresholds on input associated with output under test and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Rev. 1.6 (V) Conditions Typ. ...

Page 5

... OLD (5) Output Current I OHD I Maximum Quiescent CC Supply Current Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. ©1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Rev. 1.6 (V) Conditions Typ. CC 4.5 V 0.1V or 1.5 ...

Page 6

... Data Clock Pulse Width, HIGH or LOW Pulse Width, HIGH or LOW W t Recovery Time rec Note: 7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V. ©1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Rev. 1.6.0 T +25° 50pF L (6) V (V) Min. ...

Page 7

... Recovery Time Note: 9. Voltage range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter C Input Capacitance IN C Power Dissipation Capacitance for AC PD Power Dissipation Capacitance for ACT ©1988 Fairchild Semiconductor Corporation 74AC273, 74ACT273 Rev. 1.6.0 T +25° 50pF L (8) V (V) Min. Typ. Max. ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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