cy28443oxc-3t SpectraLinear Inc, cy28443oxc-3t Datasheet - Page 2

• Manufacturer Part Number: cy28443oxc-3t
• Description: Clock Generator Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 20, 2006
Pin Descriptions
1, 7, 11, 21,
28, 34, 42, 48
2, 6, 13, 29,
45, 51
3,4
5
8
9
10
12
14, 15
16
17,18
19,20,22,23,
24,25,30,31
26,27
33,32
36,35
37
38
39
44,43,41,40
46
47
49
50
Pin No.
SRC[T/C]5_SATA
VDD
VSS
PCI[3:4]
PCI5/FCTSEL1
ITP_SEL/PCIF0
PCIF1
VTT_PWRGD#/PD
FSA/48M
DOT96T/27M_non
spread
DOT96C/27M_Spread
FSB
SRC[T/C]0/
100M[T/C]_SST
SRC[T/C]
SRCT9/CLKREQ#A,
SRCC9/CLKREQ#B
CPUT2_ITP/SRCT11,
CPUC2_ITP/SRCC11
VDDA
VSSA
IREF
CPU[T/C][0:1]
SCLK
SDATA
XOUT
XIN
Name
I/O, SE 3.3V LVTTL input to enable SRC[T/C]11or CPU[T/C]2_ITP/33-MHz clock
I/O, SE 33-MHz clock.
I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) / 100-MHz
O, DIF Fixed 96-MHz Differential Clock/ Single ended 27-MHz clocks. When
O, DIF 100-MHz Differential Serial Reference Clocks.
O, DIF Differential serial reference clock. Recommended output for SATA.
O, DIF Selectable differential CPU / SRC clock output.
O, DIF Differential CPU clock outputs.
O, SE 33-MHz clock.
O, SE
O,DIF 100-MHz Differential Serial Reference Clock/ 100-MHz LVDS Differential
O, SE 14.318-MHz crystal output.
PWR 3.3V power supply.
PWR 3.3V power supply for PLL.
GND
I, PU
GND
Type
OD
PD
I/O
I/O
I
I
I
I
Ground.
33-MHz clock/3.3 LVTTL input for selecting for pin 14, 15 (DOT96[T/C],
27M-non-spread and Spread) and pin 17,18 (SRC[T/C]0 or 100M[T/C]_SST)
(sampled on the VTT_PWRGD# assertion).
output. (sampled on the VTT_PWRGD# assertion).
1 = CPU_ITP, 0 = SRC11
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS[C:A],
ITP_SEL, FCTSEL[1:0], SEL_CLKREQ#. After VTT_PWRGD# (active LOW)
assertion, this pin becomes a real-time input for asserting power-down (active
HIGH).
3.3V-tolerant input for CPU frequency selection/Fixed 48-MHz clock output.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications.
configured for 27-MHz, only the clock on pin 15 contains spread. Selected via
FCTSEL[0:1] at VTT_PWRGD# assertion.
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications
Clock.
Serial Reference Clock.
Default function is CLKREQ#
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC11,
ITP_EN = 1@ VTT_PWRGD# assertion =CPU2_ITP
Ground for PLL.
A precision resistor is attached to this pin, which is connected to the internal
current reference.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
14.318-MHz crystal input.
FCTSEL1 FCTSEL0 PIN 14
0
0
1
1
0
1
0
1
DOT96T
DOT96T
27M_non spread 27M_Spread SRCT0
OFF Low
Description
PIN 15
DOT96C
DOT96C
TBD
PIN 17
100MT_SST 100MC_SST
SRCT0
SRCT0
CY28443-3
PIN 18
SRCC0
SRCC0
SRCC0
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