cy2sstv850oct SpectraLinear Inc, cy2sstv850oct Datasheet - Page 6

• Manufacturer Part Number: cy2sstv850oct
• Description: Differential Clock Buffer/driver
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 21, 2006
AC Parameters
Note:
12. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
13. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle = t
14. Refers to transition of non-inverting output.
15. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
16. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 6.
17. DUT refers to Device Under Test.
11. Parameters are guaranteed by design and characterization. Not 100% tested in production.
f
t
t
t
tp
tp
t
t
t
t
t
t
t
CLK
DC
lock
R
CCJ
t
PLH
PHL
SK(0)
PHASE
JITT(PHASE)
d(0)
jit(h-per)
/t
ZL
LZ
spread of –0.5%.
the cycle time (t
Parameter
F
, tp
, tp
ZH
HZ
C
) decreases as the frequency goes up.
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time
(all outputs)
Output Disable Time
(all outputs)
Cycle to Cycle Jitter
Half-period jitter
Low-to-High Propagation Delay,
CLKINT to YT[0:9]
High-to-Low Propagation Delay,
CLKINT to YT[0:9]
Any Output to Any Output Skew
Phase Error
Phase Error Jitter
Dynamic Phase Offset
[11, 12]
(V
DD
[16]
= V
Description
DDQ
[15]
[14]
[14]
= 2.5V±5%, V
[13]
[16]
DDI
= 3.3V±5%, T
A
20% to 80% of VOD
f > 66 MHz
f > 66 MHz
f > 66 MHz
CLKIN pins to FBIN pins at the
DUT
VDD
[17]
, V
DD
Conditions
= 2.5V ± 0.2V
A
= 0°C to +70°C)
–100
–100
–150
Min.
–50
1.5
1.5
60
40
30
1
CY2SSTV850
Typ.
3.5
3.5
3
3
Page 6 of 9
Max.
170
100
100
100
100
150
140
60
50
2
6
6
WH
/t
C
MHz
Unit
V/ns
, where
μs
ns
ns
ps
ps
ns
ns
ps
ps
ps
ps
%