cy2sstu32864 SpectraLinear Inc, cy2sstu32864 Datasheet - Page 6

• Manufacturer Part Number: cy2sstu32864
• Description: 1.8v, 25-bit 14-bit Jedec-compliant Data Register
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 25, 2006
I
C
F
T
T
T
T
T
T
T
T
S
Notes:
DC Electrical Specifications
AC Timing Specifications
DDD
dv/dt
Parameter
4. Data and V
5. Data, V
ACT
rPHL
CLK
W
INACT
SU
H
PDM
PDMS
LR
IN
Parameter
[4,5]
[4,5]
REF
REF
and clock inputs must be held at valid levels (not floating) a minimum time of T
Power Supply Current
Dynamic Operating Clock
Only
Dynamic Operating per
each Data Input
Low Power Active Mode,
CLK only
Low Power Active Mode
per each Data Input
Ci (Data)
Ci (CK and CK#)
Ci (RESET#)
inputs must be low a minimum time of T
Description
Clock Frequency
Pulse Duration
Differential Input Active Time
Differential Input Inactive Time
Set up Time
Hold Time
Propagation Delay without Switching
Propagation Delay with Switching
Propagation Delay from High to Low
Slew Rate Falling
Delta between Rising/Falling Rates
Slew Rate Rising
Description
(continued)
RESET# = V
CK# switching 50% duty cycle,
V
RESET# = V
CK# switching 50% duty cycle,
V
RESET# = V
CK# switching 50% duty cycle,
V
RESET# = V
CK# switching 50% duty cycle,
V
RESET# = V
CK# switching 50% duty cycle,
V
CS Enabled
RESET# = V
CK# switching 50% duty cycle,
V
CS Enabled
V
V
V
DD
DD
DD
DD
DD
DD
I
IX
I
= V
= V
= 0.9V, V
= 1.8V, 1 IO switching 1:1 configuration,
= 1.8V, 1 IO switching 1:2 configuration;
= 1.8V
= 1.8V, 1 IO switching 1:1 configuration
= 1.8V, 1 IO switching 1:2 configuration
= 1.8V, CS Enabled
ACT
DD
REF
max, after RESET# is taken high.
or GND
± 250 mV
DD
DD
DD
DD
DD
DD
ID
= 600 mV
, V
, V
, V
, V
, V
, V
Conditions
I
I
I
I
I
I
= V
= V
= V
= V
= V
= V
CK,CK# H or L
DCS# before crossing CK,CK#,
CSR = H, CK going high
DCS# before crossing CK,CK#,
CSR = L, CK going high
CSR, ODT, CKE and data
before crossing CK,CK#, CK
going high
DCS#, CSRT#, ODT, CKE and
data after crossing CK,CK#, CK
going high
From CK, CK# to Q
From CK, CK# to Q –
simultaneous switching
RESET# Start to Q Low
dv/dt_r (20 to 80%)
dv/dt_f (20 to 80%)
IH(AC)
IH(AC)
IH(AC)
IH(AC)
IH(AC)
IH(AC)
or V
or V
or V
or V
or V
or V
Conditions
INACT
IL(AC)
IL(AC)
IL(AC)
IL(AC)
IL(AC)
IL(AC)
max after RESET# is taken low.
, CK,
, CK,
, CK,
, CK,
, CK,
, CK,
Min.
2.5
2
28 (typical)
18 (typical)
36 (typical)
27 (typical)
CY2SSTU32864
2 (typical)
2 (typical)
Min.
0.7
0.5
0.5
0.5
–
1
–
–
1
1
–
2.5
Max.
3.5
3
Max.
1.86
1.87
Page 6 of 9
500
10
15
–
–
–
–
–
3
4
4
1
A/MHz
A/MHz
A/MHz
A/MHz
A/MHz
A/MHz
Unit
MHz
pF
pF
pF
Unit
V/ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns