mtd20p06hdl Freescale Semiconductor, Inc, mtd20p06hdl Datasheet

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mtd20p06hdl

Manufacturer Part Number
mtd20p06hdl
Description
Tm Data Sheet Hdtmos E-fet Tm High Density Power Fet Dpak For Surface Mount
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Designer's
HDTMOS E-FET
High Density Power FET
DPAK for Surface Mount
P–Channel Enhancement–Mode Silicon Gate
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for low–voltage,
high–speed switching applications in power supplies, converters
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola Inc.
TMOS is a registered trademark of Motorola Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
MAXIMUM RATINGS
Motorola TMOS Power MOSFET Transistor Device Data
Drain–Source Voltage
Drain–Gate Voltage (R GS = 1.0 M )
Gate–Source Voltage — Continuous
Gate–Source Voltage
Drain Current — Continuous
Drain Current
Drain Current
Total Power Dissipation
Total Power Dissipation @ T C = 25 C (1)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting T J = 25 C
Thermal Resistance — Junction to Case
Thermal Resistance
Thermal Resistance
Maximum Temperature for Soldering Purposes, 1/8 from case for 10 seconds
This advanced high–cell density HDTMOS E–FET is designed to
Motorola, Inc. 1995
Ultra Low R DS(on) , High–Cell Density, HDTMOS
Diode is Characterized for Use in Bridge Circuits
I DSS and V DS(on) Specified at Elevated Temperature
Avalanche Energy Specified
Surface Mount Package Available in 16 mm, 13–inch/2500
Unit, Tape & Reel, Add T4 Suffix to Part Number
Derate above 25 C
(V DD = 25 Vdc, V GS = 5.0 Vdc, I L = 15 Apk, L = 2.7 mH, R G = 25 )
— Continuous @ 100 C
— Single Pulse (t p
— Junction to Ambient
— Junction to Ambient (1)
— Non–Repetitive (t p
(T C = 25 C unless otherwise noted)
Data Sheet
10 s)
Rating
10 ms)
G
D
S
Symbol
T J , T stg
V GSM
V DGR
V DSS
R JC
R JA
R JA
V GS
E AS
I DM
P D
T L
I D
I D
MTD20P06HDL
CASE 369A–13, Style 2
TMOS POWER FET
R DS(on) = 175 M
Motorola Preferred Device
– 55 to 150
LOGIC LEVEL
15 AMPERES
Value
0.58
1.75
1.73
71.4
300
100
260
9.0
Order this document
60 VOLTS
60
60
15
45
72
by MTD20P06HDL/D
DPAK
15
20
Watts
Watts
W/ C
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
C/W
mJ
C
C
1

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mtd20p06hdl Summary of contents

Page 1

... Preferred devices are Motorola recommended choices for future use and best overall value. REV 1  Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1995 D G Rating 10 ms) Order this document by MTD20P06HDL/D MTD20P06HDL Motorola Preferred Device TMOS POWER FET LOGIC LEVEL 15 AMPERES 60 VOLTS R DS(on) = 175 M  CASE 369A–13, Style 2 ...

Page 2

... MTD20P06HDL ELECTRICAL CHARACTERISTICS ( 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain–Source Breakdown Voltage ( Vdc 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current ( Vdc Vdc Vdc Vdc 125°C) Gate–Body Leakage Current ( ±15 Vdc ...

Page 3

... Figure 4. On–Resistance versus Drain Current 100 100 125 150 DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 6. Drain–To–Source Leakage MTD20P06HDL 25° – 55°C 100° DRAIN CURRENT (AMPS) and Gate Voltage 125° ...

Page 4

... MTD20P06HDL Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals ( t) are deter- mined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculat- ing rise and fall because drain– ...

Page 5

... In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses 25°C 0.75 1 1.25 1.5 1. SOURCE–TO–DRAIN VOLTAGE (Volts) MTD20P06HDL d(off) t d(on) 10 100 GATE RESISTANCE (Ohms) 2.25 2.5 5 ...

Page 6

... MTD20P06HDL The Forward Biased Safe Operating Area curves define the maximum simultaneous drain–to–source voltage and drain current that a transistor can handle safely when it is for- ward biased. Curves are based upon maximum peak junc- tion temperature and a case temperature ( 25°C. Peak ...

Page 7

... DUTY CYCLE 1.0E–03 1.0E–02 1.0E–01 t, TIME (s) Figure 14. Thermal Response di/ 0. Figure 15. Diode Reverse Recovery Waveform MTD20P06HDL R JC ( CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME J(pk) – (pk (t) 1.0E+00 1.0E+01 TIME 7 ...

Page 8

... MTD20P06HDL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface 0.190 4 ...

Page 9

... Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D 2 PAK is not recommended for wave soldering. MTD20P06HDL Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 10

... MTD20P06HDL For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next ...

Page 11

... Motorola TMOS Power MOSFET Transistor Device Data PACKAGE DIMENSIONS SEATING –T– PLANE STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE DRAIN CASE 369A–13 ISSUE W MTD20P06HDL NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.235 0.250 5.97 6.35 B ...

Page 12

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 *MTD20P06HDL/D* Motorola TMOS Power MOSFET Transistor Device Data MTD20P06HDL/D ...

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