mtd8n06e Freescale Semiconductor, Inc, mtd8n06e Datasheet - Page 4

• Manufacturer Part Number: mtd8n06e
• Description: Tm Data Sheet Tmos E-fet.tm Power Field Effect Transistor Dpak For Surface Mount
• Manufacturer: Freescale Semiconductor, Inc

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals ( t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies great-
ly with applied voltage. Accordingly, gate charge data is used.
In most cases, a satisfactory estimate of average input current
(I G(AV) ) can be made from a rudimentary analysis of the drive
circuit so that
t = Q/I G(AV)
During the rise and fall time interval when switching a resistive
load, V GS remains virtually constant at a level known as the
plateau voltage, V SGP . Therefore, rise and fall times may be
approximated by the following:
t r = Q 2 x R G /(V GG – V GSP )
t f = Q 2 x R G /V GSP
where
V GG = the gate drive voltage, which varies from zero to V GG
R G = the gate drive resistance
and Q 2 and V GSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage
change in an RC network. The equations are:
t d(on) = R G C iss In [V GG /(V GG – V GSP )]
t d(off) = R G C iss In (V GG /V GSP )
MTD8N06E
Switching behavior is most easily modeled and predicted
4
1200
1000
800
600
400
200
0
10
C iss
C rss
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
POWER MOSFET SWITCHING
V DS = 0 V
5
V GS
Figure 7. Capacitance Variation
0
V DS
V GS = 0 V
5
C rss
The capacitance (C iss ) is read from the capacitance curve at a
voltage corresponding to the off–state condition when calcu-
lating t d(on) and is read at a voltage corresponding to the on–
state when calculating t d(off) .
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
At high switching speeds, parasitic circuit elements com-
The resistive switching time variation versus gate resis-
Motorola TMOS Power MOSFET Transistor Device Data
10
C oss
C iss
15
T J = 25°C
20
25