stw5093 STMicroelectronics, stw5093 Datasheet
stw5093
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stw5093 Summary of contents
Page 1
... The PCM interface sup- ports both non-delayed (normal and reverse) and de- layed frame synchronization modes. STw5093 can be configurated either as a 14-bit lin- ear 8-bit companded PCM coder. Additionally to the CODEC/FILTER function, STw5093 includes a Tone/Ring/DTMF generator, a sidetone gen- eration, and a buzzer driver output ...
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... STw5093 PIN CONNECTIONS (Top view) REMOUT BLOCK DIAGRAM MIC PREAMP 0/20dB MIC3- + MUTE MIC2- PG MIC1- MIC2+ MIC1+ MIC3+ VS & TE EARA OUTPUT 0 -> -30dB, 2dB STEP VFr 6dB OE VLr- -1 12dB VLr+ 1 EXTA OUTPUT MICROPHONE MBIAS BIAS MB D98TL408 2/ REMIN 3 28 ...
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... Chip Select input: When this pin is low, control information is written into and out from the STw5093 via CI and CO pins Control data Input: Serial Control information is shifted into the STw5093 on this pin when CS- is low on the rising edges of CCLK. 23 AUXCLK Auxiliary Clock Input. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CR0 ...
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... N° Pin 24 VCCIO Power supply Input for the Digital I/O' Control data Output: Serial control/status information is shifted out from the STw5093 on this pin when CS- is low on the falling edges of CCLK. 26 GND Ground: All digital signals are referenced to this pin Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots. ...
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... Following power-on initialization, power up and power down control may be accomplished by writing any of the control instructions listed in Table 1 into STw5093 with "P" bit set to 0 for power for power down. Normally recommended that all programmable functions be initially programmed while the device is pow- ered down ...
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... STw5093 mit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de- layed reverse mode.A separate MBIAS output can be used to bias a microphone (bit register CR10) 1.1.5 Receive section: Voice Data is shifted into the decoder's Receive voice data Register via the DR pin during the selected time slot on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MCLK in non- delayed reverse mode ...
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... Table 1, with the exception of a single byte power-up/down command. To shift control data into STw5093, CCLK must be pulsed high 8 times while CS- is low. Data on CI input is shifted into the serial input register on the rising edge of each CCLK pulse. After all data is shifted in, the content of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow ...
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... STw5093 To read-back status information from STw5093, the first byte of the appropriate instruction is strobed in during the first CS- pulse, as defined in Table 1. CS- must be set low for a further 8 CCLK cycles, during which data is shifted out of the CO pin on the falling edges of CCLK. When CS- is high, CO pin is in the high impedance Tri-state, enabling CO pins of several devices to be multi- plexed together ...
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... STW5093 Data byte none see CR0 TABLE see CR0 see CR1 TABLE see CR1 see CR2 TABLE 4 ...
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... STw5093 Table 2. Control Register CR0 Functions state at power on initialization (1): significant in companded mode only Table 3. Control Register CR1 Functions DM1 DM0 ...
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... Receive output muted VFr output selected VLr output selected NOT ALLOWED 0 Ring / Tone Ring / Tone Receive High Pass filter enabled 1 Receive High Pass filter disabled 0 Receive Signal Receive Signal to V STW5093 Function Function Function * * * or V disabled * enabled Fr Lr ...
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... STw5093 Table 7. Control Register CR5 Functions Transmit amplifier Sidetone amplifier state at power on initialization Table 8. Control Register CR6 Functions Earpiece ampifier Extra amplifier [EXTA] [EARA ...
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... BZ1 BZ0 Buzzer output disabled (set to 0) Buzzer output enabled Duty Cycle is intended as the relative width of logic 1 Duty cycle is intended as the relative width of logic 0 lsb Binary equivalent of the decimal number used to calculate the duty cycle. STW5093 Function Function Function * * * * * ...
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... B1 and B2 channel are separated by two bits. (See digital interface format section.) 56+8 selection (1) Bit 'B7' (1) selects capability for STw5093 to take into account only the seven most significant bits of the PCM data byte selected. When 'B7' is set, the LSB bit ignored and LSB bit high impedance. This function allows con- nection of an external " ...
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... MSB is always the first PCM bit shifted in or out of: STw5093. Transmit/Receive enabling/disabling Bit 'EN' (2) enables or disables voice data transfer on DX and DR pins. When disabled, PCM data from DR is not decoded and PCM time-slots are high impedance on DX. Default value is disabled. ...
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... STw5093 Transmit Input Selection MIC1 or MIC2 or MIC3 or transmit mute can be selected with bits 6 and 7 (VS and TE). Transmit gain can be adjusted within a 22.5 dB range in 1.5 dB step with Register CR5. Sidetone Selection Bit "SI" (5) enables or disables Sidetone circuitry. When enabled, sidetone gain can be adjusted with Register (CR5) ...
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... First byte of a READ or a WRITE instruction to Control Register CR8 or CR9 is as shown in TABLE 1. Second byte is respectively as shown in TABLE 10 and 11. If "standard frequency tone range" is selected, Tone or Ring signal frequency value is defined by the formula: and V 1.965 Vrms when 0 dB gain is selected down Lr+ Lr CR8 / 0.128 Hz STW5093 17/34 ...
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... STw5093 and where CR8 and CR9 are decimal equivalents of the binary values of the CR8 and CR9 registers respectively. Thus, any frequency between 7.8 Hz and 1992 Hz may be selected in 7.8 Hz step. If "halved frequency tone range"is selected, Tone or Ring signal frequency value is defined by the formula: and This any frequency between 3 ...
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... STW5093 Typical value (Hz) Error% 250 -.00 328.2 -.56 421.9 -.73 437.5 -.56 796.9 -.39 1328.1 -.14 695.3 -.24 773.4 +.44 851.6 -.05 937.5 -.37 1210.9 +.16 1335.9 -.01 1476.6 .00 1632.8 .00 390.6 - ...
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... STw5093 TIMING DIAGRAM Figure 2. Non Delayed Data Timing Mode (Normal) (*) Figure 3. Delayed Data Timing Mode (*) (*) In the case of companded code the timing is applied to 8 bits instead of 16 bits. 20/34 ...
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... FS tDFD tDMDR (*) In the case of companded code the timing is applied to 8 bits instead of 16 bits. Figure 5. Serial Control Timing (MICROWIRE MODE) tRM tFM tSDM tHMDR tWMM tWML D93TL076A STW5093 17 tDMZR 21/34 ...
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... STw5093 ABSOLUTE MAXIMUM RATINGS V to GND CC ≤ 3.3V) Voltage at MIC (V CC Current at V and Current at any digital output Voltage at any digital input (V CCIO Storage temperature range Lead Temperature (wave soldering, 10s) OPERATIVE SUPPLY VOLTAGES Symbol CCA CCP V CCIO TIMING SPECIFICATIONS (unless otherwise specified, V ...
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... Non Delayed Mode only R Load = 20pF R Test Condition Measured from Measured from Measured from Measured from Load = 20pF STW5093 Min. Typ. Max. Unit 10 100 ns 100 100 ns 10 100 ...
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... STw5093 TIMING SPECIFICATIONS (continued) SERIAL CONTROL PORT TIMING (continued) Symbol Parameter t Delay Time CS-high or 8th CCLK DDZ low to CO high impedance whichever comes first t Hold Time, 8th CCLK high to CS- HSC high t Set up Time, CS- high to CCLK SCS high Note 5: A signal is valid above V ...
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... DR ±1mA Lr+ Lr- from Lr+ Lr- Steady zero PCM code applied to DR; I ± 1mA , Alternating ± zero PCM code Lr+ applied to DR maximum receive gain 50Ω L STW5093 0.7V CCIO 0.3V CCIO D93TL077A for a logic "0". Min. Typ. Max. 150 -100 +100 1.0 8 ...
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... STw5093 TRANSMISSION CHARACTERISTICS (unless otherwise specified, V typical characteristics are specified 1015.625 Hz; all signal are referenced to GND) AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Transmit path - Absolute levels at MIC1 / MIC2 / MIC3 Symbol Parameter 0 dBm0 level Overload level 0 dBm0 level Overload level ...
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... Maximum to minimum setting.Calculate the deviation from the programmed gain relative RAL i. RAGL actual prog. RAL Measured relative to GRA and min. gain < G < Max. gain R STW5093 Min. Typ. Max. Unit - -1.5 0.5 dB -0.5 0.5 dB -1.5 0.0 dB -14 dB -35 ...
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... STw5093 AMPLITUDE RESPONSE(continued) Receive path (continued) Symbol Parameter G Receive Gain Variation with RAV Supply G Receive Gain Variation with RAF frequency (V and HPB = 0 Receive Gain Variation with frequency (V and HPB = 1 G Receive Gain Variation with RAL E signal level ( Receive Gain Variation with ...
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... Hz Input PCM Code applied 4600 Hz - 5600 Hz 5600 Hz - 7600 Hz 7600 Hz - 8400 Hz Test Condition Transmit Level = 0 dBm0 300 - 3400 Quiet PCM Code R Receive Level = -6 dBm0 300 - 3400 Hz MIC = 0V STW5093 Min. Typ. Max. Unit µs 320 µs 290 µs 180 µs 50 µs 20 µ ...
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... STw5093 DISTORTION Symbol Parameter S (*) Signal to Total Distortion TDX (up to 35dB gain) Typical values are measured with 30.5dB gain S Single Frequency Distortion transmit DFx S (*) Signal to Total Distortion (V TDRE ( up to 20dB attenuation) Typical values are measured with 20dB attenuation. S Single Frequency Distortion DFr ...
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... For highes capacitor transducers, lower R values can be used MBIAS STw5093 MICP 22µF MICN 1KΩ D98TL395 Connections Connections STW5093 DIFFERENTIAL MODE MBIAS 1KΩ STw5093 2KΩ 4KΩ MICP 0.47µF MICN 4KΩ 0.47µF D98TL396 DYNAMIC RECEIVERS (8Ω) V Lr+ STw5093 V Lr- D98TL398 DYNAMIC RECEIVERS (30Ω) C=100µ STw5093 D98TL410 31/34 ...
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... Low cost strategy: tie analog and digital power supplies together as close as possible to GND and VCC pins. This allows to use only one set of capacitors between VCC and GND. Figure 11. 32/34 AVCC VCCP VCC VCCA 100nF STw5093 AGND AGND GNDP GNDA GND AGND D98TL412 VCCP VCC VCCA 100nF STw5093 GNDP GNDA GND DVCC 100nF DGND DGND 10µF D98TL413 ...
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... SEATING PLANE D 30 Pin 1 identification inch TYP. MAX. 0.043 0.006 0.035 0.037 0.011 0.008 0.307 0.311 0.252 0.0197 0.173 0.177 0.024 0.028 TSSOP30 (Thin Shrink SEATING PLANE STW5093 OUTLINE AND MECHANICAL DATA E1 c Gage Plane 0.25mm A1 L TSSO30M k 33/34 ...
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... STW5093 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...