MX29L3211 Macronix International, MX29L3211 Datasheet - Page 10

• Manufacturer Part Number: MX29L3211
• Description: CMOS SINGLE VOLTAGE PAGEMODE FLASH EEPROM
• Manufacturer: Macronix International

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A6 specify the word address withih the page. The byte
(word) may be loaded in any order; sequential loading is
not required. If a high to low transition of CE or WE is not
detected whithin 100us of the last low to high transition,
the load period will end and the internal programming
period will start. The Auto page program terminates
when status on Q7 is '1' at which time the device stays
at read status register mode until the CIR contents are
altered by a valid command sequence.(Refer to table
3,6 and Figure 1,7,8)
CHIP ERASE
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command-80H. Two more "unlock" write cycles
are then followed by the chip erase command-10H.
Chip erase does not require the user to program the
device prior to erase.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the status on Q7 is "1" at which time the device
stays at read status register mode. The device remains
enabled for read status register mode until the CIR
contents are altered by a valid command sequence.(Refer
to table 3,6 and Figure 2,7,9)
Table 5. MX29L3211 Sector Address Table
P/N:PM0641
SA0
SA1
SA2
SA3
SA4
SA31
A20
0
0
0
0
0
...
1
(Word-Wide Mode)
A19
0
0
0
0
0
...
1
A18
0
0
0
0
1
...
1
A17
0
0
1
1
0
...
1
A16
0
1
0
1
0
1
...
Address Range[A20,A0]
000000H--00FFFFH
010000H--01FFFFH
020000H--02FFFFH
030000H--03FFFFH
040000H--04FFFFH
1F0000H--1FFFFFH
................................
10
SECTOR ERASE
Sector erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command (data) is latched on the rising edge
of WE.
Sector erase does not require the user to program the
device prior to erase. The system is not required to
provide any controls or timings during these operations.
The automatic sector erase begins on the rising edge of
the last WE pulse in the command sequence and
terminates when the status on Q7 is "1" at which time the
device stays at read status register mode. The device
remains enabled for read status register mode until the
CIR contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 3,4,7,9)
ERASE SUSPEND
This command only has meaning while the the WSM is
executing SECTOR or CHIP erase operation, and
therefore will only be responded to during SECTOR or
CHIP erase operation. After this command has been
executed, the CIR will initiate the WSM to suspend erase
operations, and then return to Read Status Register
mode. The WSM will set the Q6 bit to a "1". Once the
WSM has reached the Suspend state,the WSM will set
the Q7 bit to a "1", At this time, WSM allows the CIR to
respond to the Read Array, Read Status Register, Abort
and Erase Resume commands only. In this mode, the
CIR will not resopnd to any other comands. The WSM
will continue to run, idling in the SUSPEND state,
regardless of the state of all input control pins.
ERASE RESUME
This command will cause the CIR to clear the suspend
state and set the Q6 to a '0', but only if an Erase Suspend
command was previously issued. Erase Resume will
not have any effect in all other conditions.
MX29L3211
REV. 0.3, NOV. 06, 2001