MX25L4005 Macronix International, MX25L4005 Datasheet - Page 4

• Manufacturer Part Number: MX25L4005
• Description: 4M-BIT [x 1] CMOS SERIAL FLASH
• Manufacturer: Macronix International

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DATA PROTECTION
• Power-On Reset and an internal timer (tPUW) can
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• All instructions that modify data must be preceded by
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P/N: PM1236
provide protection against inadvertant changes while
the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions
are checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
a Write Enable (WREN) instruction to set the Write
Enable Latch (WEL) bit . This bit is returned to its reset
state by the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of
the memory to be configured as readonly. This is the
Software Protected Mode (SPM).
The Write Protect (WP#) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status Register
Write Disable (SRWD) bit to be protected. This is the
Hardware Protected Mode (HPM).
In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protec-
tion from inadvertent Write, Program and Erase in-
structions, as all instructions are ignored except one
particular instruction (the Release from Deep
Powerdown instruction).
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• To avoid unexpected changes by system power supply
• Before the Program, Erase, and Write Status Register
• Write Enable (WREN) instruction must set to Write
• The Software Protected Mode (SPM) use (BP2, BP1,
• The Hardware Protected Mode (HPM) use WP# to
• Deep-Power Down Mode also protects the device by
transition, the Power-On Reset and an internal timer
(tPUW) can protect the device.
execution, instruction length will be checked on follow-
ing the clock pulse number to be multiple of eight base.
Enable Latch (WEL) bit before writing other instructions
to modify data. The WEL bit will return to reset state by
following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
BP0) bits to allow part of memory to be protected as
read only.
protect the (BP2, BP1, BP0) bits and SRWD bit.
ignoring all instructions except Release from Deep-
Power Down (RDP) instruction and RES instruction.
MX25L4005
REV. 1.1, SEP. 30, 2005