MX25L3205A Macronix International, MX25L3205A Datasheet - Page 37

• Manufacturer Part Number: MX25L3205A
• Description: 32M-BIT [x 1] CMOS SERIAL eLiteFlash MEMORY
• Manufacturer: Macronix International

Figure 33. READ STATUS REGISTER TIMING SEQUENCE (Parallel)
NOTES:
1. 1st Byte='05h'
2. BIT7 status register write disable signal. BIT7=1, means SR write disable.
3. BIT6=0 ==> Program/erase is correct.
4. BIT4, 3, 2 defines the level of protected block. (BIT 5 is not used)
5. BIT1 write enable latch
6. BIT0=0 ==> Device is in ready state
7. Under parallel mode, the fastest access clock freq. will be changed to 1.2MHz(SCLK pin clock freq.).
8. In serial RDID and RDSR mode, output pin SO will be enabled at 8th clock's rising edge. That means, MXIC's drip will
P/N: PM1243
Once in the parallel mode, eLiteFlash
To read status register in parallel mode requires a parallel mode command (55H) before the read status register
command.
enable output half a cycle in advance compare with other compatible vendor's spec.
TM
Memory will not exit parallel mode until power-off.
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MX25L3205A
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REV. 1.2, NOV. 06, 2006