MBM29F033C Fujitsu Media Devices, MBM29F033C Datasheet - Page 20

• Manufacturer Part Number: MBM29F033C
• Description: 32M (4M X 8) BIT
• Manufacturer: Fujitsu Media Devices

20
MBM29F033C
DQ
Toggle Bit I
DQ
Exceeded Timing Limits
DQ
Sector Erase Timer
Just prior to the completion of Embedded Algorithm operation DQ
enable (OE) is asserted low. This means that the device is driving status information on DQ
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations
and DQ
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See Table 7.)
See Figure 8 for the Data Polling timing specifications and diagrams.
The MBM29F033C also features the “Toggle Bit I” as a method to indicate to the host system that the embedded
algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device at any address will result in DQ
Erase Algorithm cycle is completed, DQ
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the
six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of the sector erase
WE pulse. The Toggle Bit I is active during the sector erase time out.
Either CE or OE toggling will cause the DQ
cause DQ
DQ
these conditions DQ
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will
control the output disable functions as described in Table 2.
The DQ
to 0. In this case the device locks out and never completes the Embedded Program
system never reads a valid data on DQ
limits, the DQ
incorrectly used. If this occurs, reset the device.
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ
be used to determine if the sector erase timer window is still open. If DQ
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ
6
5
3
5
will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
7
5
failure condition may also appear if a user tries to program a 1 to a location that is previously programmed
has a valid data, the data outputs on DQ
6
to toggle. See Figure 9 for the Toggle Bit I timing specifications and diagrams.
5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was
5
will produce a “1”. This is a failure condition which indicates that the program or erase
-70/-90/-12
7
bit and DQ
6
will stop toggling and valid data will be read on the next successive
6
6
toggling between one and zero. Once the Embedded Program or
to toggle. In addition, an Erase Suspend/Resume command will
0
6
to DQ
never stops toggling. Once the device has exceeded timing
6
may be still invalid. The valid data on DQ
7
may change asynchronously while the output
3
is high (“1”) the internally controlled
TM
Algorithm. Hence, the
7
at one instant of
3
0
is low (“0”),
to DQ
3
may
7
3
will
will
7