MBM29DL400BC Fujitsu Media Devices, MBM29DL400BC Datasheet - Page 14
![no-image](/images/no-image-200.jpg)
MBM29DL400BC
Manufacturer Part Number
MBM29DL400BC
Description
4M (512K X 8/256K X 16) BIT
Manufacturer
Fujitsu Media Devices
Datasheet
1.MBM29DL400BC.pdf
(56 pages)
- Current page: 14 of 56
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14
MBM29DL400TC
RESET
Hardware Reset
The MBM29DL400TC/BC devices may be reset by driving the RESET pin to V
requirement and has to be kept low (V
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional t
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing
diagram. Refer to Temporary Sector Unprotection for additional functionality.
RH
-55/-70/-90/-12
before it will allow read access. When the RESET pin is low, the devices will
IL
) for at least 500 ns in order to properly reset the internal state machine.
/MBM29DL400BC
IL
. The RESET pin has a pulse
-55/-70/-90/-12
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