RM5261A-250-H PMC-Sierra Inc, RM5261A-250-H Datasheet - Page 25

• Manufacturer Part Number: RM5261A-250-H
• Description: RM5261A Microprocessor with 64-Bit System Bus Data Sheet Preliminary
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002240, Issue 2
3.28 Interrupt Handling
3.29 Standby Mode
3.30 JTAG Interface
3.31 Boot-Time Options
The RM5261A supports a dedicated interrupt vector. When enabled by the real time executive (by
setting a bit in the Cause register), interrupts vector to a specific address that is not shared with any
of the other exception types. This capability eliminates the need to go through the normal software
routine for exception decode and dispatch, thereby lowering interrupt latency.
The RM5261A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
Executing the WAIT instruction enables interrupts and causes the processor to enter Standby
Mode. If the SysAD bus is idle when the wait instruction completes the W pipe stage, the internal
processor clock stops and the pipeline is suspended. The phase lock loop, or PLL, internal timer/
counter, and the “wake up” input pins: Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*
continue to operate in their normal fashion. If the SysAD bus is not idle when the WAIT
instruction completes the W pipe-stage, then the WAIT is treated as a NOP until the bus operation
is completed. Once the processor is in Standby, any interrupt, including the internally generated
timer interrupt, causes the processor to exit Standby mode and resume operation where it left off.
The WAIT instruction is typically inserted in the idle loop of the operating system or real time
executive.
The RM5261A interface supports JTAG Test Access Port (TAP) boundary scan in conformance
with the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the
integrity of the processors pin connections.
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. This serial interface operates at a very low frequency (SysClock divided by 256). The
low frequency operation allows the initialization information to be kept in a low cost EPROM or
system interface ASIC.
Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits
to initialize all the fundamental operational modes. ModeClock runs continuously from the
assertion of VccOK.
RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
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