RM5231A-350-H PMC-Sierra Inc, RM5231A-350-H Datasheet - Page 26

• Manufacturer Part Number: RM5231A-350-H
• Description: RM5231A Microprocessor with 32-Bit System Bus Data Sheet Preliminary
• Manufacturer: PMC-Sierra Inc

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
3.27 External Requests
3.28 Interrupt Handling
3.29 Standby Mode
3.30 JTAG Interface
3.31 Boot-Time Options
In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined
writes have the same two bus cycle write repeat rate, but can issue one additional write following
the deassertion of
The External Request pin, ExtRqst*, is asserted by the external agent when it requires mastership
of the system interface, either to perform an independent transfer or to write to the interrupt
register within the RM5231A. An independent transfer is a data transfer between two external
agents or between an external agent and memory or peripheral on the system interface. Following
the asserting of the ExtRqst*, the RM5231A tri-states its drivers allowing the external agent to
use the system interface buses to complete an independent transfer. The external agent is
responsible for returning mastership of the system interface to the RM5231A when it has
completed the independent transfer and does so by executing an External Null cycle.
The RM5231A supports a dedicated interrupt vector for real time interrupt handling. When
enabled by the real time executive by setting a bit in the Cause register, interrupts vector to a
specific address which is not shared with any of the other exception types. This capability
eliminates the need to go through the normal software routine for exception decode and dispatch,
thereby lowering interrupt latency.
The RM5231A provides a means to reduce the amount of power consumed by the internal core
when the CPU is not performing any useful operations. This state is known as Standby Mode.
Executing the WAIT instruction enables interrupts causes the processor to enter Standby Mode.
When the WAIT instruction completes the W pipe stage, and if the SysAD bus is currently idle, the
internal processor clocks stop, thereby freezing the pipeline. The phase lock loop, or PLL, internal
timer/counter, and the “wake up” input pins: Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset*
continue to operate in their normal fashion. If the SysAD bus is not idle when the WAIT
instruction completes the W pipe-stage, then the WAIT is treated as a NOP until the bus operation
is completed. Once the processor is in Standby, any interrupt, including the internally generated
timer interrupt, causes the processor to exit Standby and resume operation where it left off. The
WAIT instruction is typically inserted in the idle loop of the operating system or real time
executive.
The RM5231A interface supports JTAG Test Access Port (TAP) boundary scan in conformance
with the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the
integrity of the processors pin connections.
Fundamental operational modes for the processor are initialized by the boot-time mode control
interface. This serial interface operates at a very low frequency (SysClock divided by 256). The
low frequency operation allows the initialization information to be kept in a low cost EPROM or a
system interface ASIC.
WrRdy*
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RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Preliminary
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