NT256D64S88B1G Nanya Technology, NT256D64S88B1G Datasheet - Page 10

• Manufacturer Part Number: NT256D64S88B1G
• Description: (NT256D64S88Bxx) 256MB DDR DIMM
• Manufacturer: Nanya Technology

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G
NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G
NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)
Unbuffered DDR DIMM
Serial Presence Detect
SPD Description
REV 2.2
Aug 3, 2004
Preliminary
Byte
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
0
1
2
3
4
5
6
7
8
9
Description
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Rank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time
CL=2.5
DDR SDRAM Device Access Time from Clock
CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
DDR SDRAM Device Attributes: Burst Length
Supported
DDR SDRAM Device Attributes: Number of Device
Banks
DDR SDRAM Device Attributes:
CAS Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle
CL=2.5
Maximum Data Access Time from Clock at
CL=2
Minimum Clock Cycle Time at CL=1
10
99-127
36-40
46-61
64-71
73-90
93-94
95-98
91-92
Byte
26
27
28
29
30
31
32
33
34
35
41
42
43
44
45
62
63
72
Minimum Row Precharge Time (t
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Minimum Active/Auto-refresh Time (t
Auto-refresh to Active/Auto-refresh Command Period
(t
Max Cycle Time (t
Maximum DQS-DQ Skew Time (t
Maximum Read Data Hold Skew Factor (t
Module Part number
Module Manufacturing Data
yy= Binary coded decimal year code, 0-99(Decimal),
00-63(Hex)
ww= Binary coded decimal year code, 01-52(Decimal),
01-34(Hex)
Reserved
Description
Maximum Data Access Time from Clock at CL=1
Minimum Row Active to Row Active delay (t
Minimum RAS to CAS delay (t
Minimum RAS Pulse Width (t
Module Bank Density
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
Reserved
SPD Revision
Checksum Data
Manufacturer’s JEDEC ID Code
Module Manufacturing Location
Module Revision Code
Module Serial Number
RFC
NANYA reserves the right to change products and specifications without notice.
)
CK max
)
© NANYA TECHNOLOGY CORPORATION
RAS
RCD
)
RP
DQSQ
)
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RC
)
)
QHS
RRD
)
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