LTC6905 Linear Technology, LTC6905 Datasheet - Page 5

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LTC6905

Manufacturer Part Number
LTC6905
Description
17MHz to 170MHz Resistor Set SOT-23 Oscillator
Manufacturer
Linear Technology
Datasheet

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BLOCK DIAGRA
THEORY OF OPERATIO
As shown in the Block Diagram, the LTC6905’s master
oscillator is controlled by the ratio of the voltage between
the V
(I
mately 1V below V
bias voltage.
A resistor R
“locks together” the voltage (V
variation. This provides the LTC6905’s high precision. The
master oscillation frequency reduces to:
To extend the output frequency range, the master oscilla-
tor signal is divided by 1, 2 or 4 before driving OUT (Pin
5). The LTC6905 is optimized for use with resistors
between 10k and 25k, corresponding to oscillator fre-
quencies between 17.225MHz and 170MHz. The divide-
by value is determined by the state of the DIV input
(Pin 4). Tie DIV to V
select ÷1. This is the highest frequency range, with the
RES
f
MO
I
R
). The voltage on the SET pin is forced to approxi-
+
RES
SET
and SET pins and the current entering the SET pin
=
168 5
1
3
2
GND
SET
V
SET
+
.
+
, connected between the V
MHz
R
V
SET
BIAS
+
by the PMOS transistor and its gate
+
10
+
or drive it to within 0.4V of V
k
W
+
+
1 5
– V
.
MHz
SET
U
) and current, I
I
+
RES
GAIN = 1
+
and SET pins,
V
RES
(V
+
= 1V ±5%
– V
RES
+
SET
to
)
,
MASTER OSCILLATOR
master output frequency passed directly to OUT. The DIV
pin may be floated or driven to midsupply to select ÷2, the
intermediate frequency range. The lowest frequency range,
÷4, is selected by tying DIV to GND or driving it below
0.5V. Figure 1 shows the relationship between R
divider setting and output frequency, including the over-
lapping frequencies.
30
25
20
15
10
5
10
Figure 1. R
÷4 ÷2
OUTPUT FREQUENCY (MHz)
60
SET
÷1
DIVIDER
SELECT
PROGRAMMABLE
vs Output Frequency
INPUT DETECT
THREE-STATE
110
(÷1, 2 OR 4)
DIVIDER
160
6905 F01
f
OSC
LTC6905
=
GND
f
V
MO
N
+
15µA
15µA
OUT
DIV
6905 BD
5
4
6905fa
SET
5
,

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