LTC4011 Linear Technology, LTC4011 Datasheet - Page 21

• Manufacturer Part Number: LTC4011
• Description: High Efficiency Standalone Nickel Battery Charger
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
that programs the correct number of series cells when it
is connected to the charger, along with indicating chem-
istry and providing temperature information.
Any of these battery pack charge control concepts could
be combined in a variety of ways to service custom
application needs.
PCB Layout Considerations
To prevent magnetic and electrical field radiation and high
frequency resonant problems, proper layout of the com-
ponents connected to the LTC4011 is essential. Refer to
Figure 13. For maximum efficiency, the switch node rise
and fall times should be minimized. The following PCB
design priority list will help ensure proper topology. Lay-
out the PCB using this specific order.
4
Figure 12. NiMH Battery Pack Indicating Number of Cells
V
IN
C
Figure 13. High Speed Switching Path
IN
CHEM
SWITCHING GROUND
4
CIRCULATING
FREQUENCY
V
SWITCH NODE
U
TEMP
HIGH
PATH
7
10k
NTC
V
U
CELL
8
R2
+
–
W
L1
1500mAhr
NiMH CELLS
D1
BATTERY
PACK
4011 F12
C
OUT
U
4011 F13
BAT
V
BAT
1. Input capacitors should be placed as close as possible
2. Place the LTC4011 close to the switching FET gate
3. Place the inductor input as close as possible to the
4. Place the charge current sense resistor immediately
5. Place output capacitors adjacent to the sense resisitor
6. Output capacitor ground connections must feed into
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
terminals, keeping the connecting traces short to
produce clean drive signals. This rule also applies to
IC supply and ground pins that connect to the switch-
ing FET source pins. The IC can be placed on the
opposite side of the PCB from the switching FETs.
drain of the switching FETs. Minimize the surface area
of the switch node. Make the trace width the minimum
needed to support the programmed charge current.
Use no copper fills or pours. Avoid running the con-
nection on multiple copper layers in parallel. Minimize
capacitance from the switch node to any other trace or
plane.
adjacent to the inductor output, and orient it such that
current sense traces to the LTC4011 are short. These
feedback traces need to be run together as a single pair
with the smallest spacing possible on any given layer
on which they are routed. Locate any filter component
on these traces next to the LTC4011, and not at the
sense resistor location.
output and ground.
the same copper that connects to the input capacitor
ground before tying back into system ground.
LTC4011
21
4011p