LTC3788-1 Linear Technology, LTC3788-1 Datasheet - Page 23

• Manufacturer Part Number: LTC3788-1
• Description: Dual Output Synchronous Boost Controller
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
2. Are the signal and power grounds kept separate? The
3. Do the LTC3788-1 VFB pins’ resistive dividers connect to
4. Are the SENSE
5. Is the INTV
6. Keep the switching nodes (SW1, SW2), top gate nodes
7. Use a modifi ed “star ground” technique: a low imped-
combined IC signal ground pin and the ground return of
C
The path formed by the bottom N-channel MOSFET and
the C
lengths. The output capacitor (–) terminals should be
connected as close as possible to the (–) terminals of
the input capacitor by placing the capacitors next to
each other.
the (+) terminals of C
connected between the (+) terminal of C
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
minimum PC trace spacing? The fi lter capacitor between
SENSE
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
to the IC, between the INTV
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV
improve noise performance substantially.
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3788-1 and occupy a minimal
PC trace area.
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
INTVCC
IN
+
capacitor should have short leads and PC trace
must return to the combined C
and SENSE
CC
–
decoupling capacitor connected close
and SENSE
OUT
–
should be as close as possible
? The resistive divider must be
+
CC
leads routed together with
CC
and PGND pins can help
and the power ground
OUT
OUT
(–) terminals.
and signal
CC
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
drops below the low current operation threshold— typi-
cally 10% of the maximum designed current level in Burst
Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for its individual performance should
both controllers be turned on at the same time. A particu-
larly diffi cult region of operation is when one controller
channel is nearing its current comparator trip point while
the other channel is turning on its bottom MOSFET. This
occurs around the 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
Reduce V
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering V
the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
IN
from its nominal level to verify operation with
LTC3788-1
IN
while monitoring
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